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| author | Marek Vasut <[email protected]> | 2024-04-05 20:21:53 +0000 |
|---|---|---|
| committer | Shawn Guo <[email protected]> | 2024-04-22 04:33:30 +0000 |
| commit | 10947b276b90df38e60aa3efd6b4b7a4b3c92fab (patch) | |
| tree | 8db6246a3d0a737bacb510fb55413522f4634149 /drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | |
| parent | arm64: dts: imx8qm-ss-dma: fix can lpcg indices (diff) | |
| download | kernel-10947b276b90df38e60aa3efd6b4b7a4b3c92fab.tar.gz kernel-10947b276b90df38e60aa3efd6b4b7a4b3c92fab.zip | |
arm64: dts: imx8mp: Fix assigned-clocks for second CSI2
The first CSI2 pixel clock are supplied from IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT,
the second CSI2 pixel clock are supplied from IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT,
both clock are supplied from SYS_PLL2 and configured using assigned-clock DT
properties. Each CSI2 DT node configures its IMX8MP_CLK_MEDIA_CAMn_PIX_ROOT
clock. This used to be the case until likely a copy-paste error in commit
f78835d1e616 ("arm64: dts: imx8mp: reparent MEDIA_MIPI_PHY1_REF to CLK_24M")
which changed the second CSI2 node to configure IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT
using its assigned-clocks property.
Fix the second CSI2 assigned-clock property back to the original correct
IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT .
Fixes: f78835d1e616 ("arm64: dts: imx8mp: reparent MEDIA_MIPI_PHY1_REF to CLK_24M")
Signed-off-by: Marek Vasut <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c')
0 files changed, 0 insertions, 0 deletions