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| author | Dapeng Mi <[email protected]> | 2025-05-29 08:02:36 +0000 |
|---|---|---|
| committer | Ingo Molnar <[email protected]> | 2025-05-31 08:05:16 +0000 |
| commit | 86aa94cd50b138be0dd872b0779fa3036e641881 (patch) | |
| tree | d0372bbd912135c68c82279e9a4baeab62863bea /drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | |
| parent | Merge tag 'x86_sev_for_v6.16_rc1' of git://git.kernel.org/pub/scm/linux/kerne... (diff) | |
| download | kernel-86aa94cd50b138be0dd872b0779fa3036e641881.tar.gz kernel-86aa94cd50b138be0dd872b0779fa3036e641881.zip | |
perf/x86/intel: Fix incorrect MSR index calculations in intel_pmu_config_acr()
The MSR offset calculations in intel_pmu_config_acr() are buggy.
To calculate fixed counter MSR addresses in intel_pmu_config_acr(),
the HW counter index "idx" is subtracted by INTEL_PMC_IDX_FIXED.
This leads to the ACR mask value of fixed counters to be incorrectly
saved to the positions of GP counters in acr_cfg_b[], e.g.
For fixed counter 0, its ACR counter mask should be saved to
acr_cfg_b[32], but it's saved to acr_cfg_b[0] incorrectly.
Fix this issue.
[ mingo: Clarified & improved the changelog. ]
Fixes: ec980e4facef ("perf/x86/intel: Support auto counter reload")
Signed-off-by: Dapeng Mi <[email protected]>
Signed-off-by: Ingo Molnar <[email protected]>
Reviewed-by: Kan Liang <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c')
0 files changed, 0 insertions, 0 deletions