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| author | Chris Wilson <[email protected]> | 2020-11-02 22:10:57 +0000 |
|---|---|---|
| committer | Rodrigo Vivi <[email protected]> | 2020-11-04 00:22:42 +0000 |
| commit | e67d01d8494640018b08cd767aeb2824a8e11983 (patch) | |
| tree | 1dbb48f036ec19d7c855d97d38e9db3494692e89 /drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | |
| parent | drm/i915/gt: Expose more parameters for emitting writes into the ring (diff) | |
| download | kernel-e67d01d8494640018b08cd767aeb2824a8e11983.tar.gz kernel-e67d01d8494640018b08cd767aeb2824a8e11983.zip | |
drm/i915/gt: Flush xcs before tgl breadcrumbs
In a simple test case that writes to scratch and then busy-waits for the
batch to be signaled, we observe that the signal is before the write is
posted. That is bad news.
Splitting the flush + write_dword into two separate flush_dw prevents
the issue from being reproduced, we can presume the post-sync op is not
so post-sync.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/216
Testcase: igt/gem_exec_fence/parallel
Testcase: igt/i915_selftest/live/gt_timelines
Signed-off-by: Chris Wilson <[email protected]>
Cc: Mika Kuoppala <[email protected]>
Cc: [email protected]
Acked-by: Mika Kuoppala <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
(cherry picked from commit 09212e81e5450743e5b06b27c4e344e4c45b630d)
Signed-off-by: Rodrigo Vivi <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c')
0 files changed, 0 insertions, 0 deletions