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authorDibin Moolakadan Subrahmanian <[email protected]>2025-05-28 06:45:56 +0000
committerJoonas Lahtinen <[email protected]>2025-06-04 14:30:53 +0000
commit791d76005de0ab556b590473eb4cbfede727fce0 (patch)
tree71cd0d88b611ff84ed697b43ef059d69e2b5c823 /drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
parentdrm/i915/guc: Handle race condition where wakeref count drops below 0 (diff)
downloadkernel-791d76005de0ab556b590473eb4cbfede727fce0.tar.gz
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drm/i915/display: Fix u32 overflow in SNPS PHY HDMI PLL setup
When configuring the HDMI PLL, calculations use DIV_ROUND_UP_ULL and DIV_ROUND_DOWN_ULL macros, which internally rely on do_div. However, do_div expects a 32-bit (u32) divisor, and at higher data rates, the divisor can exceed this limit. This leads to incorrect division results and ultimately misconfigured PLL values. This fix replaces do_div calls with div64_base64 calls where diviser can exceed u32 limit. Fixes: 5947642004bf ("drm/i915/display: Add support for SNPS PHY HDMI PLL algorithm for DG2") Cc: Ankit Nautiyal <[email protected]> Cc: Suraj Kandpal <[email protected]> Cc: Jani Nikula <[email protected]> Signed-off-by: Dibin Moolakadan Subrahmanian <[email protected]> Reviewed-by: Ankit Nautiyal <[email protected]> Signed-off-by: Ankit Nautiyal <[email protected]> Link: https://lore.kernel.org/r/[email protected] (cherry picked from commit ce924116e43ffbfa544d82976c4b9d11bcde9334) Signed-off-by: Joonas Lahtinen <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c')
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