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| author | Ethan Milon <[email protected]> | 2025-07-14 04:50:27 +0000 |
|---|---|---|
| committer | Will Deacon <[email protected]> | 2025-07-14 10:18:04 +0000 |
| commit | 3141153816bf4f0257747bd4dda176d38f1a9a49 (patch) | |
| tree | 1abfcd10fac04f18311cc77d71a381a92bd31258 /drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | |
| parent | iommu/vt-d: Split paging_domain_compatible() (diff) | |
| download | kernel-3141153816bf4f0257747bd4dda176d38f1a9a49.tar.gz kernel-3141153816bf4f0257747bd4dda176d38f1a9a49.zip | |
iommu/vt-d: Fix missing PASID in dev TLB flush with cache_tag_flush_all
The function cache_tag_flush_all() was originally implemented with
incorrect device TLB invalidation logic that does not handle PASID, in
commit c4d27ffaa8eb ("iommu/vt-d: Add cache tag invalidation helpers")
This causes regressions where full address space TLB invalidations occur
with a PASID attached, such as during transparent hugepage unmapping in
SVA configurations or when calling iommu_flush_iotlb_all(). In these
cases, the device receives a TLB invalidation that lacks PASID.
This incorrect logic was later extracted into
cache_tag_flush_devtlb_all(), in commit 3297d047cd7f ("iommu/vt-d:
Refactor IOTLB and Dev-IOTLB flush for batching")
The fix replaces the call to cache_tag_flush_devtlb_all() with
cache_tag_flush_devtlb_psi(), which properly handles PASID.
Fixes: 4f609dbff51b ("iommu/vt-d: Use cache helpers in arch_invalidate_secondary_tlbs")
Fixes: 4e589a53685c ("iommu/vt-d: Use cache_tag_flush_all() in flush_iotlb_all")
Signed-off-by: Ethan Milon <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Lu Baolu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Will Deacon <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c')
0 files changed, 0 insertions, 0 deletions
