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| author | Lucas De Marchi <[email protected]> | 2021-06-22 21:22:09 +0000 |
|---|---|---|
| committer | Lucas De Marchi <[email protected]> | 2021-06-25 16:04:08 +0000 |
| commit | cbeeb00f14d2bf71200cbfad329a62be6309f7e2 (patch) | |
| tree | 576fdaf391419f93b2c56467c173ce89d090a557 /drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | |
| parent | drm/i915/display/adl_p: Implement Wa_16011303918 (diff) | |
| download | kernel-cbeeb00f14d2bf71200cbfad329a62be6309f7e2.tar.gz kernel-cbeeb00f14d2bf71200cbfad329a62be6309f7e2.zip | |
drm/i915/display: fix level 0 adjustement on display ver >= 12
We should no longer increment level 0 by 1usec when we have 16Gb DIMMs.
Instead spec says to add 3usec (as opposed to 2) to each valid level
when punit replies 0 to level 0.
So set wm_lv_0_adjust_needed to false for DISPLAY_VER() >= 12 and set
the proper adjustment value when handling WaWmMemoryReadLatency.
Bspec: 49326, 4381
Signed-off-by: Lucas De Marchi <[email protected]>
Reviewed-by: Matt Roper <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c')
0 files changed, 0 insertions, 0 deletions