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authorVineet Gupta <[email protected]>2016-09-28 18:53:17 +0000
committerVineet Gupta <[email protected]>2017-11-21 23:21:08 +0000
commit82385732b1c9d6a22942b5fe6e48a99891cb806f (patch)
treecf0c5e5c0ca3f7490eaab51f8346368d24875e9c /drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
parentARCv2: perf: optimize given that num counters <= 32 (diff)
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ARC: perf: avoid vmalloc backed mmap
For non-alising Dcache, vmalloc is not needed. vmalloc triggers additonal D-TLB Misses in the perf interrupt code path making it slightly inefficient as evident from hackbench runs below. | [ARCLinux]# perf stat -e dTLB-load-misses --repeat 5 hackbench | Running with 10*40 (== 400) tasks. | Time: 35.060 | ... | Performance counter stats for 'hackbench' (5 runs): Before: 399235 dTLB-load-misses ( +- 2.08% ) After : 397676 dTLB-load-misses ( +- 2.27% ) Acked-by: Peter Zijlstra (Intel) <[email protected]> Signed-off-by: Vineet Gupta <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c')
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