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| author | Samson Tam <[email protected]> | 2022-09-09 21:16:32 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2022-09-27 22:00:01 +0000 |
| commit | 2d3907c152611a0d65efe54b93972320dcce1565 (patch) | |
| tree | c4b10f6cf37817c8d52e5a06f15d81202216d41a /drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | |
| parent | drm/amd/display: Avoid unnecessary pixel rate divider programming (diff) | |
| download | kernel-2d3907c152611a0d65efe54b93972320dcce1565.tar.gz kernel-2d3907c152611a0d65efe54b93972320dcce1565.zip | |
drm/amd/display: fill in clock values when DPM is not enabled
[Why]
For individual feature testing, PMFW may not report all clock
values back. Driver will default them to 0 but this will
cause the BB table to be skipped and default to one state
with max clocks.
[How]
Add helper function to scan through initial clock values and
populate them with default clock limits so that BB table
can be built.
Add dpm_enabled flag to check when DPM is not enabled and
to trigger helper function.
Reviewed-by: Jun Lei <[email protected]>
Acked-by: Jasdeep Dhillon <[email protected]>
Signed-off-by: Samson Tam <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c')
0 files changed, 0 insertions, 0 deletions