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| author | Govindraj Raja <[email protected]> | 2016-02-29 11:41:20 +0000 |
|---|---|---|
| committer | Ralf Baechle <[email protected]> | 2016-02-29 14:44:23 +0000 |
| commit | 56fa81fc9a5445938f3aa2e63d15ab63dc938ad6 (patch) | |
| tree | 6cd4ed3f609f2ed8e4c2bfd69b1e16280eaf4a22 /drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | |
| parent | MIPS: Avoid variant of .type unsupported by LLVM Assembler (diff) | |
| download | kernel-56fa81fc9a5445938f3aa2e63d15ab63dc938ad6.tar.gz kernel-56fa81fc9a5445938f3aa2e63d15ab63dc938ad6.zip | |
MIPS: scache: Fix scache init with invalid line size.
In current scache init cache line_size is determined from
cpu config register, however if there there no scache
then mips_sc_probe_cm3 function populates a invalid line_size of 2.
The invalid line_size can cause a NULL pointer deference
during r4k_dma_cache_inv as r4k_blast_scache is populated
based on line_size. Scache line_size of 2 is invalid option in
r4k_blast_scache_setup.
This issue was faced during a MIPS I6400 based virtual platform bring up
where scache was not available in virtual platform model.
Signed-off-by: Govindraj Raja <[email protected]>
Fixes: 7d53e9c4cd21("MIPS: CM3: Add support for CM3 L2 cache.")
Cc: Paul Burton <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: James Hartley <[email protected]>
Cc: [email protected]
Cc: [email protected] # v4.2+
Patchwork: https://patchwork.linux-mips.org/patch/12710/
Signed-off-by: Ralf Baechle <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_display.c')
0 files changed, 0 insertions, 0 deletions