diff options
| author | Tao Zhou <[email protected]> | 2023-10-18 09:57:25 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2023-10-20 19:11:28 +0000 |
| commit | 21226f02d77b6a1efcf987df8d97b2a4f40087bd (patch) | |
| tree | da65b3b096d10f0ebb9fdf62802b86d8678f6f27 /drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | |
| parent | drm/amdgpu: add clockgating support for NBIO v7.7.1 (diff) | |
| download | kernel-21226f02d77b6a1efcf987df8d97b2a4f40087bd.tar.gz kernel-21226f02d77b6a1efcf987df8d97b2a4f40087bd.zip | |
drm/amdgpu: replace reset_error_count with amdgpu_ras_reset_error_count
Simplify the code.
Signed-off-by: Tao Zhou <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_device.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 0f98f720d9ca..2d385476939b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3578,9 +3578,7 @@ static void amdgpu_device_xgmi_reset_func(struct work_struct *__work) if (adev->asic_reset_res) goto fail; - if (adev->mmhub.ras && adev->mmhub.ras->ras_block.hw_ops && - adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count) - adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev); + amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB); } else { task_barrier_full(&hive->tb); @@ -5201,9 +5199,7 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle, if (!r && amdgpu_ras_intr_triggered()) { list_for_each_entry(tmp_adev, device_list_handle, reset_list) { - if (tmp_adev->mmhub.ras && tmp_adev->mmhub.ras->ras_block.hw_ops && - tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count) - tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(tmp_adev); + amdgpu_ras_reset_error_count(tmp_adev, AMDGPU_RAS_BLOCK__MMHUB); } amdgpu_ras_intr_cleared(); |