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| author | Radim Krčmář <[email protected]> | 2025-07-25 16:54:09 +0000 |
|---|---|---|
| committer | Paul Walmsley <[email protected]> | 2025-09-05 21:30:45 +0000 |
| commit | e108c8a94f3f958c877f6ec7a6052a893ae4aa98 (patch) | |
| tree | e33d461885923e5983e9e8b5f75e20f37ec46975 /drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | |
| parent | ACPI: RISC-V: Fix FFH_CPPC_CSR error handling (diff) | |
| download | kernel-e108c8a94f3f958c877f6ec7a6052a893ae4aa98.tar.gz kernel-e108c8a94f3f958c877f6ec7a6052a893ae4aa98.zip | |
riscv: use lw when reading int cpu in new_vmalloc_check
REG_L is wrong, because thread_info.cpu is 32-bit, not xlen-bit wide.
The struct currently has a hole after cpu, so little endian accesses
seemed fine.
Fixes: 503638e0babf ("riscv: Stop emitting preventive sfence.vma for new vmalloc mappings")
Cc: [email protected]
Reviewed-by: Alexandre Ghiti <[email protected]>
Signed-off-by: Radim Krčmář <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paul Walmsley <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c')
0 files changed, 0 insertions, 0 deletions