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| author | Chunyan Zhang <[email protected]> | 2025-03-05 08:37:06 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <[email protected]> | 2025-06-05 21:03:07 +0000 |
| commit | 6093faaf9593fca92f96f165c95ff4b53353b1f4 (patch) | |
| tree | 6ad368038e4c7657fbde3cc61e732db5a4e909b4 /drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | |
| parent | riscv: mm: Add support for Svinval extension (diff) | |
| download | kernel-6093faaf9593fca92f96f165c95ff4b53353b1f4.tar.gz kernel-6093faaf9593fca92f96f165c95ff4b53353b1f4.zip | |
raid6: Add RISC-V SIMD syndrome and recovery calculations
The assembly is originally based on the ARM NEON and int.uc, but uses
RISC-V vector instructions to implement the RAID6 syndrome and
recovery calculations.
The functions are tested on QEMU running with the option "-icount shift=0":
raid6: rvvx1 gen() 1008 MB/s
raid6: rvvx2 gen() 1395 MB/s
raid6: rvvx4 gen() 1584 MB/s
raid6: rvvx8 gen() 1694 MB/s
raid6: int64x8 gen() 113 MB/s
raid6: int64x4 gen() 116 MB/s
raid6: int64x2 gen() 272 MB/s
raid6: int64x1 gen() 229 MB/s
raid6: using algorithm rvvx8 gen() 1694 MB/s
raid6: .... xor() 1000 MB/s, rmw enabled
raid6: using rvv recovery algorithm
[Charlie: - Fixup vector options]
Signed-off-by: Charlie Jenkins <[email protected]>
Signed-off-by: Chunyan Zhang <[email protected]>
Reviewed-by: Charlie Jenkins <[email protected]>
Tested-by: Charlie Jenkins <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Ghiti <[email protected]>
Signed-off-by: Palmer Dabbelt <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c')
0 files changed, 0 insertions, 0 deletions