diff options
| author | Dave Airlie <[email protected]> | 2022-05-19 04:09:46 +0000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2022-05-19 04:09:54 +0000 |
| commit | 00df0514ab13813655a6fbaba85425f8f4780be2 (patch) | |
| tree | 85e9e8908b702575ff4a7e4a58cf36dcca93c204 /drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | |
| parent | Merge branch 'etnaviv/next' of https://git.pengutronix.de/git/lst/linux into ... (diff) | |
| parent | drm/amd: Don't reset dGPUs if the system is going to s2idle (diff) | |
| download | kernel-00df0514ab13813655a6fbaba85425f8f4780be2.tar.gz kernel-00df0514ab13813655a6fbaba85425f8f4780be2.zip | |
Merge tag 'amd-drm-next-5.19-2022-05-18' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-5.19-2022-05-18:
amdgpu:
- Misc code cleanups
- Additional SMU 13.x enablement
- Smartshift fixes
- GFX11 fixes
- Support for SMU 13.0.4
- SMU mutex fix
- Suspend/resume fix
amdkfd:
- static checker fix
- Doorbell/MMIO resource handling fix
Signed-off-by: Dave Airlie <[email protected]>
From: Alex Deucher <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c index 494ca6a0f47a..63e0293edc5f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c @@ -556,6 +556,7 @@ bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device *adev, union smu_info { struct atom_smu_info_v3_1 v31; + struct atom_smu_info_v4_0 v40; }; union gfx_info { @@ -602,7 +603,10 @@ int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev) data_offset); /* system clock */ - spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz); + if (frev == 3) + spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz); + else if (frev == 4) + spll->reference_freq = le32_to_cpu(smu_info->v40.core_refclk_10khz); spll->reference_div = 0; spll->min_post_div = 1; |