diff options
| author | Jani Nikula <[email protected]> | 2024-06-19 08:38:31 +0000 |
|---|---|---|
| committer | Jani Nikula <[email protected]> | 2024-06-19 08:38:31 +0000 |
| commit | d754ed2821fd9675d203cb73c4afcd593e28b7d0 (patch) | |
| tree | cd16683cd956a7c334d7e1b3baf02e2e7baa729c /drivers/gpu/drm/amd/amdgpu/amdgpu.h | |
| parent | intel_alpm: Fix wrong offset for PORT_ALPM_* registers (diff) | |
| parent | Merge tag 'amd-drm-next-6.11-2024-06-07' of https://gitlab.freedesktop.org/ag... (diff) | |
| download | kernel-d754ed2821fd9675d203cb73c4afcd593e28b7d0.tar.gz kernel-d754ed2821fd9675d203cb73c4afcd593e28b7d0.zip | |
Merge drm/drm-next into drm-intel-next
Sync to v6.10-rc3.
Signed-off-by: Jani Nikula <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu.h')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu.h | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index f87d53e183c3..35faa286bb1c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -220,6 +220,8 @@ extern int amdgpu_discovery; extern int amdgpu_mes; extern int amdgpu_mes_log_enable; extern int amdgpu_mes_kiq; +extern int amdgpu_uni_mes; +extern int amdgpu_jpeg_test; extern int amdgpu_noretry; extern int amdgpu_force_asic_type; extern int amdgpu_smartshift_bias; @@ -253,10 +255,12 @@ extern int amdgpu_cik_support; extern int amdgpu_num_kcq; #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) +#define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024) extern int amdgpu_vcnfw_log; extern int amdgpu_sg_display; extern int amdgpu_umsch_mm; extern int amdgpu_seamless; +extern int amdgpu_umsch_mm_fwlog; extern int amdgpu_user_partt_mode; extern int amdgpu_agp; @@ -341,9 +345,9 @@ enum amdgpu_kiq_irq { AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, AMDGPU_CP_KIQ_IRQ_LAST }; -#define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ -#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ -#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ +#define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ +#define MAX_KIQ_REG_WAIT (amdgpu_sriov_vf(adev) ? 50000 : 5000) /* in usecs, extend for VF */ +#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ #define MAX_KIQ_REG_TRY 1000 int amdgpu_device_ip_set_clockgating_state(void *dev, @@ -1014,6 +1018,7 @@ struct amdgpu_device { /* jpeg */ struct amdgpu_jpeg jpeg; + bool enable_jpeg_test; /* vpe */ struct amdgpu_vpe vpe; @@ -1046,6 +1051,7 @@ struct amdgpu_device { /* mes */ bool enable_mes; bool enable_mes_kiq; + bool enable_uni_mes; struct amdgpu_mes mes; struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; @@ -1161,6 +1167,7 @@ struct amdgpu_device { bool debug_largebar; bool debug_disable_soft_recovery; bool debug_use_vram_fw_buf; + bool debug_enable_ras_aca; }; static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, |