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| author | Alex Deucher <[email protected]> | 2024-09-12 17:08:12 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2024-09-18 20:15:06 +0000 |
| commit | 797fb1533315571ff9e55e80154f48cd47f3dbe5 (patch) | |
| tree | c4714b2c8e4319e1836efab5b85fe2aac6098e9a /drivers/gpu/drm/amd/amdgpu/amdgpu.h | |
| parent | drm/amdgpu: Fix selfring initialization sequence on soc24 (diff) | |
| download | kernel-797fb1533315571ff9e55e80154f48cd47f3dbe5.tar.gz kernel-797fb1533315571ff9e55e80154f48cd47f3dbe5.zip | |
drm/amdgpu/gfx9.4.3: set additional bits on MEC halt
Need to set the pipe reset and cache invalidation bits
on halt otherwise we can get stale state if the CP firmware
changes (e.g., on module unload and reload).
Tested-by: Amber Lin <[email protected]>
Reviewed-by: Amber Lin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu.h')
0 files changed, 0 insertions, 0 deletions