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| author | Daniel Machon <[email protected]> | 2024-12-20 13:48:47 +0000 |
|---|---|---|
| committer | Jakub Kicinski <[email protected]> | 2024-12-23 18:57:56 +0000 |
| commit | 010fe5dff1644f60520302fd43776a54402b623f (patch) | |
| tree | 1addc8e9ab736ebd7e9f9370b9ca8bdb5faeab2b /drivers/fpga/xilinx-spi.c | |
| parent | net: lan969x: add RGMII registers (diff) | |
| download | kernel-010fe5dff1644f60520302fd43776a54402b623f.tar.gz kernel-010fe5dff1644f60520302fd43776a54402b623f.zip | |
net: lan969x: add RGMII implementation
The lan969x switch device includes two RGMII port interfaces (port 28
and 29) supporting data speeds of 1 Gbps, 100 Mbps and 10 Mbps. MAC
level delays are configurable through the HSIO_WRAP target, by choosing
a phase shift selector, corresponding to a certain time delay in nano
seconds.
Add new file: lan969x_rgmii.c that contains the implementation for
configuring the RGMII port devices. MAC level delays are configured
using the "{rx,tx}-internal-delay-ps" properties. These properties must
be specified independently of the phy-mode. If missing, or set to zero,
the MAC will not apply any delay.
Reviewed-by: Steen Hegelund <[email protected]>
Reviewed-by: Horatiu Vultur <[email protected]>
Tested-by: Robert Marko <[email protected]>
Signed-off-by: Daniel Machon <[email protected]>
Link: https://patch.msgid.link/20241220-sparx5-lan969x-switch-driver-4-v5-8-fa8ba5dff732@microchip.com
Signed-off-by: Jakub Kicinski <[email protected]>
Diffstat (limited to 'drivers/fpga/xilinx-spi.c')
0 files changed, 0 insertions, 0 deletions