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authorJohn David Anglin <[email protected]>2021-11-08 21:48:16 +0000
committerHelge Deller <[email protected]>2021-11-13 21:10:56 +0000
commit38860b2c8bb1b92f61396eb06a63adff916fc31d (patch)
tree121428c7e59fe17646c82b4fcd3196cf83b9ed68 /drivers/fpga/xilinx-pr-decoupler.c
parentparisc: Fix implicit declaration of function '__kernel_text_address' (diff)
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parisc: Flush kernel data mapping in set_pte_at() when installing pte for user page
For years, there have been random segmentation faults in userspace on SMP PA-RISC machines. It occurred to me that this might be a problem in set_pte_at(). MIPS and some other architectures do cache flushes when installing PTEs with the present bit set. Here I have adapted the code in update_mmu_cache() to flush the kernel mapping when the kernel flush is deferred, or when the kernel mapping may alias with the user mapping. This simplifies calls to update_mmu_cache(). I also changed the barrier in set_pte() from a compiler barrier to a full memory barrier. I know this change is not sufficient to fix the problem. It might not be needed. I have had a few days of operation with 5.14.16 to 5.15.1 and haven't seen any random segmentation faults on rp3440 or c8000 so far. Signed-off-by: John David Anglin <[email protected]> Signed-off-by: Helge Deller <[email protected]> Cc: [email protected] # 5.12+
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