diff options
| author | Uwe Kleine-König <[email protected]> | 2024-05-23 10:33:25 +0000 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2024-05-23 11:35:09 +0000 |
| commit | a827ad9b3c2fc243e058595533f91ce41a312527 (patch) | |
| tree | 5917413d4ba67ab6b3912e03570b72a6eac25d95 /drivers/fpga/xilinx-core.c | |
| parent | spi: microchip-core-qspi: fix setting spi bus clock rate (diff) | |
| download | kernel-a827ad9b3c2fc243e058595533f91ce41a312527.tar.gz kernel-a827ad9b3c2fc243e058595533f91ce41a312527.zip | |
spi: stm32: Revert change that enabled controller before asserting CS
On stm32mp157 enabling the controller before asserting CS makes the
hardware trigger spurious interrupts in a tight loop and the transfers
fail. Revert the commit that swapped the order of enable and CS. This
reintroduces the problem that swapping was supposed to fix, which
however is less grave.
Reported-by: Leonard Göhrs <[email protected]>
Link: https://lore.kernel.org/all/[email protected]/
Fixes: 52b62e7a5d4f ("spi: stm32: enable controller before asserting CS")
Signed-off-by: Uwe Kleine-König <[email protected]>
Link: https://msgid.link/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'drivers/fpga/xilinx-core.c')
0 files changed, 0 insertions, 0 deletions