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| author | Shin Son <[email protected]> | 2025-04-28 11:35:15 +0000 |
|---|---|---|
| committer | Krzysztof Kozlowski <[email protected]> | 2025-04-30 07:25:22 +0000 |
| commit | 84d36f26d0314a089405af3df9e213dcfb8ecbc0 (patch) | |
| tree | 0fb27807cf4851cc47e54bdedaee2f43cf04ef92 /drivers/fpga/tests | |
| parent | Merge branch 'for-v6.16/dt-bindings-clk-samsung' into next/clk (diff) | |
| download | kernel-84d36f26d0314a089405af3df9e213dcfb8ecbc0.tar.gz kernel-84d36f26d0314a089405af3df9e213dcfb8ecbc0.zip | |
clk: samsung: exynosautov920: add cpucl1/2 clock support
Register compatible and cmu_info data to support clock CPUCL1/2
(CPU Cluster 1 and CPU Cluster 2),
these provide clock for CPUCL1/2_SWTICH/CLUSTER.
These clocks are required early during boot for the CPUs,
so they are declared using CLK_OF_DECLARE instead of being registered
through a platform driver.
Signed-off-by: Shin Son <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Diffstat (limited to 'drivers/fpga/tests')
0 files changed, 0 insertions, 0 deletions