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authorMeghana Malladi <[email protected]>2025-06-03 05:29:04 +0000
committerPaolo Abeni <[email protected]>2025-06-05 08:57:09 +0000
commit919d763d609428c2680ec8159257d9655f002f89 (patch)
tree39d8c274c1ae783628eb6ad6b4809d6b3ac8aaba /drivers/fpga/tests/fpga-mgr-test.c
parentgve: add missing NULL check for gve_alloc_pending_packet() in TX DQO (diff)
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net: ti: icssg-prueth: Fix swapped TX stats for MII interfaces.
In MII mode, Tx lines are swapped for port0 and port1, which means Tx port0 receives data from PRU1 and the Tx port1 receives data from PRU0. This is an expected hardware behavior and reading the Tx stats needs to be handled accordingly in the driver. Update the driver to read Tx stats from the PRU1 for port0 and PRU0 for port1. Fixes: c1e10d5dc7a1 ("net: ti: icssg-prueth: Add ICSSG Stats") Signed-off-by: Meghana Malladi <[email protected]> Reviewed-by: Simon Horman <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Paolo Abeni <[email protected]>
Diffstat (limited to 'drivers/fpga/tests/fpga-mgr-test.c')
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