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authorPierre-Louis Bossart <[email protected]>2025-02-27 14:06:08 +0000
committerVinod Koul <[email protected]>2025-03-10 07:01:19 +0000
commit8eb5d7ade8b1ed1678cdc5340ef3f6d346eed9be (patch)
tree4b532d1526599e15cb7c5a441fd8dfb992104a96 /drivers/fpga/tests/fpga-bridge-test.c
parentsoundwire: bus: add bpt_stream pointer (diff)
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soundwire: cadence: add BTP/BRA helpers to format data
The Cadence IP expects a specific format (detailed in the Documentation). Add helpers to copy the data into the DMA buffer. The crc8 table is for now only used by the Cadence driver. This table might be moved to a common module at a later point if needed by other controller implementations. Signed-off-by: Pierre-Louis Bossart <[email protected]> Signed-off-by: Bard Liao <[email protected]> Reviewed-by: Péter Ujfalusi <[email protected]> Reviewed-by: Liam Girdwood <[email protected]> Reviewed-by: Ranjani Sridharan <[email protected]> Tested-by: [email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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