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| author | Shin Son <[email protected]> | 2025-04-23 04:41:52 +0000 |
|---|---|---|
| committer | Krzysztof Kozlowski <[email protected]> | 2025-04-27 19:22:33 +0000 |
| commit | 59636ec89c2cafb54d33be4e288f953b0876adef (patch) | |
| tree | ec12b99bb2448fb3b8fe58eb4500237139faf409 /drivers/fpga/tests/fpga-bridge-test.c | |
| parent | Merge branch 'for-v6.16/dt-bindings-clk-samsung' into next/clk (diff) | |
| download | kernel-59636ec89c2cafb54d33be4e288f953b0876adef.tar.gz kernel-59636ec89c2cafb54d33be4e288f953b0876adef.zip | |
clk: samsung: exynosautov920: add cpucl0 clock support
Register compatible and cmu_info data to support clock CPUCL0(CPU
Cluster 0), this provides clock for CPUCL0_SWTICH/DBG/CLUSTER. These
clocks are required early during boot for the CPUs, so they are declared
using CLK_OF_DECLARE instead of being registered through a platform
driver.
Signed-off-by: Shin Son <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Diffstat (limited to 'drivers/fpga/tests/fpga-bridge-test.c')
0 files changed, 0 insertions, 0 deletions