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| author | Michael Walle <[email protected]> | 2025-08-21 12:23:41 +0000 |
|---|---|---|
| committer | Douglas Anderson <[email protected]> | 2025-09-02 16:56:05 +0000 |
| commit | bdd5a14e660062114bdebaef9ad52adf04970a89 (patch) | |
| tree | e8248644e0c17457a9b088af9e6b5d7d972801fb /drivers/fpga/microchip-spi.c | |
| parent | MAINTAINERS: Update git entry for nouveau (diff) | |
| download | kernel-bdd5a14e660062114bdebaef9ad52adf04970a89.tar.gz kernel-bdd5a14e660062114bdebaef9ad52adf04970a89.zip | |
drm/bridge: ti-sn65dsi86: fix REFCLK setting
The bridge has three bootstrap pins which are sampled to determine the
frequency of the external reference clock. The driver will also
(over)write that setting. But it seems this is racy after the bridge is
enabled. It was observed that although the driver write the correct
value (by sniffing on the I2C bus), the register has the wrong value.
The datasheet states that the GPIO lines have to be stable for at least
5us after asserting the EN signal. Thus, there seems to be some logic
which samples the GPIO lines and this logic appears to overwrite the
register value which was set by the driver. Waiting 20us after
asserting the EN line resolves this issue.
Fixes: a095f15c00e2 ("drm/bridge: add support for sn65dsi86 bridge driver")
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Douglas Anderson <[email protected]>
Signed-off-by: Douglas Anderson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'drivers/fpga/microchip-spi.c')
0 files changed, 0 insertions, 0 deletions