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| author | George Shen <[email protected]> | 2022-10-14 21:36:32 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2022-11-02 21:16:25 +0000 |
| commit | ab007e5db5d3b8b8975c7eec69992ff38fe2a46c (patch) | |
| tree | f04b6a32cc3e9da1032356379aebc55f20484dc2 /drivers/fpga/microchip-spi.c | |
| parent | drm/amd/display: Fix DCN32 DSC delay calculation (diff) | |
| download | kernel-ab007e5db5d3b8b8975c7eec69992ff38fe2a46c.tar.gz kernel-ab007e5db5d3b8b8975c7eec69992ff38fe2a46c.zip | |
drm/amd/display: Use forced DSC bpp in DML
[Why]
DSC config is calculated separately from DML calculations.
DML should use these separately calculated DSC params. The issue is
that the calculated bpp is not properly propagated into DML.
[How]
Correctly used forced_bpp value in DML.
Reviewed-by: Alvin Lee <[email protected]>
Acked-by: Alex Hung <[email protected]>
Signed-off-by: George Shen <[email protected]>
Tested-by: Mark Broadworth <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/fpga/microchip-spi.c')
0 files changed, 0 insertions, 0 deletions