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| author | Yuantian Tang <[email protected]> | 2019-04-22 09:15:08 +0000 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2019-04-25 18:22:45 +0000 |
| commit | f34b2c26fc7d120b26cb181b8d4115675ec58244 (patch) | |
| tree | 4d2c4071266a4e4e62fd48319ed5f72dda073f25 /drivers/fpga/fpga-bridge.c | |
| parent | Linux 5.1-rc1 (diff) | |
| download | kernel-f34b2c26fc7d120b26cb181b8d4115675ec58244.tar.gz kernel-f34b2c26fc7d120b26cb181b8d4115675ec58244.zip | |
dt-bindings: qoriq-clock: add more PLL divider clocks support
More PLL divider clocks are needed by clock consumer IP. So update
the PLL divider description to make it more general.
Signed-off-by: Yuantian Tang <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
0 files changed, 0 insertions, 0 deletions