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| author | Martin Blumenstingl <[email protected]> | 2021-06-27 22:39:59 +0000 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2021-06-30 18:37:02 +0000 |
| commit | e4c5ef6b9584a861210cf92955b7c8b1727688b9 (patch) | |
| tree | 0ae1068c1602cbc6cca46e1025d4d2aff361898c /drivers/fpga/fpga-bridge.c | |
| parent | clk: divider: Switch from .round_rate to .determine_rate by default (diff) | |
| download | kernel-e4c5ef6b9584a861210cf92955b7c8b1727688b9.tar.gz kernel-e4c5ef6b9584a861210cf92955b7c8b1727688b9.zip | |
clk: meson: regmap: switch to determine_rate for the dividers
This increases the maxmium supported frequency on 32-bit systems from
2^31 (signed long as used by clk_ops.round_rate, maximum value:
approx. 2.14GHz) to 2^32 (unsigned long as used by
clk_ops.determine_rate, maximum value: approx. 4.29GHz).
On Meson8/8b/8m2 the HDMI PLL and it's OD (post-dividers) are
capable of running at up to 2.97GHz. So switch the divider
implementation in clk-regmap to clk_ops.determine_rate to support these
higher frequencies on 32-bit systems.
Reviewed-by: Jerome Brunet <[email protected]>
Signed-off-by: Martin Blumenstingl <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
0 files changed, 0 insertions, 0 deletions