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| author | Martin Blumenstingl <[email protected]> | 2019-03-24 15:11:03 +0000 |
|---|---|---|
| committer | Neil Armstrong <[email protected]> | 2019-04-01 11:34:09 +0000 |
| commit | b882964b376f214ef3d96d8a643c7c46121c30a8 (patch) | |
| tree | 6dc0ac81f09c913b586d06f28dc3a91cdfecbb35 /drivers/fpga/fpga-bridge.c | |
| parent | clk: meson: meson8b: use a separate clock table for Meson8m2 (diff) | |
| download | kernel-b882964b376f214ef3d96d8a643c7c46121c30a8.tar.gz kernel-b882964b376f214ef3d96d8a643c7c46121c30a8.zip | |
clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2
Meson8m2 has a GP_PLL clock (similar to GP0_PLL on GXBB/GXL/GXM) which
is used as input for the VPU clocks.
The only supported frequency (based on Amlogic's vendor kernel sources)
is 364MHz which is achieved using the following parameters:
- input: XTAL (24MHz)
- M = 182
- N = 3
- OD = 2 ^ 2
Signed-off-by: Martin Blumenstingl <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Acked-by: Jerome Brunet <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
0 files changed, 0 insertions, 0 deletions