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| author | Weiyi Lu <[email protected]> | 2019-03-05 05:05:45 +0000 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2019-04-11 20:29:19 +0000 |
| commit | acddfc2c261b3653ab1c1b567a427299bac20d31 (patch) | |
| tree | bdacafd8bc6ece8d1219198e7eb9d4fec6743a9e /drivers/fpga/fpga-bridge.c | |
| parent | clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data (diff) | |
| download | kernel-acddfc2c261b3653ab1c1b567a427299bac20d31.tar.gz kernel-acddfc2c261b3653ab1c1b567a427299bac20d31.zip | |
clk: mediatek: Add MT8183 clock support
Add MT8183 clock support, include topckgen, apmixedsys,
infracfg, mcucfg and subsystem clocks.
Signed-off-by: Weiyi Lu <[email protected]>
Tested-by: Nicolas Boichat <[email protected]>
Reviewed-by: Nicolas Boichat <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
0 files changed, 0 insertions, 0 deletions