diff options
| author | Yash Shah <[email protected]> | 2019-05-06 10:48:40 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <[email protected]> | 2019-05-17 03:42:13 +0000 |
| commit | a967a289f16969527a8a41e261695c639a69bee4 (patch) | |
| tree | eda00cc7ecc719a9ed5e9cb82d27b64fb929d4fa /drivers/fpga/fpga-bridge.c | |
| parent | RISC-V: Add DT documentation for SiFive L2 Cache Controller (diff) | |
| download | kernel-a967a289f16969527a8a41e261695c639a69bee4.tar.gz kernel-a967a289f16969527a8a41e261695c639a69bee4.zip | |
RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs
The driver currently supports only SiFive FU540-C000 platform.
The initial version of L2 cache controller driver includes:
- Initial configuration reporting at boot up.
- Support for ECC related functionality.
Signed-off-by: Yash Shah <[email protected]>
Signed-off-by: Palmer Dabbelt <[email protected]>
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
0 files changed, 0 insertions, 0 deletions