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| author | Owen Chen <[email protected]> | 2019-03-05 05:05:40 +0000 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2019-04-11 20:13:08 +0000 |
| commit | 9d7e1a82b7d195f901c2a18dd5602a1c11e9eefb (patch) | |
| tree | c64502c6a88052a8b1857af5516b68af1d461f8d /drivers/fpga/fpga-bridge.c | |
| parent | clk: mediatek: Add new clkmux register API (diff) | |
| download | kernel-9d7e1a82b7d195f901c2a18dd5602a1c11e9eefb.tar.gz kernel-9d7e1a82b7d195f901c2a18dd5602a1c11e9eefb.zip | |
clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data
1. pcwibits: The integer bits of pcw for PLLs is extend to 8 bits,
add a variable to indicate this change and
backward-compatible.
2. fmin: The PLL frequency lower-bound is vary from 1GHz to
1.5GHz, add a variable to indicate platform-dependent.
Signed-off-by: Owen Chen <[email protected]>
Signed-off-by: Weiyi Lu <[email protected]>
Acked-by: Sean Wang <[email protected]>
Reviewed-by: James Liao <[email protected]>
Reviewed-by: Nicolas Boichat <[email protected]>
Tested-by: Nicolas Boichat <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
0 files changed, 0 insertions, 0 deletions