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| author | Sergei Shtylyov <[email protected]> | 2019-03-07 19:53:19 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2019-04-02 08:31:05 +0000 |
| commit | 21ab095cbc069a351fa9cef919f2dafc43a8fde7 (patch) | |
| tree | 576eec4a8aacf56f1383d06154768ed6d3fcf293 /drivers/fpga/fpga-bridge.c | |
| parent | clk: renesas: rcar-gen3: Rename DRIF clocks (diff) | |
| download | kernel-21ab095cbc069a351fa9cef919f2dafc43a8fde7.tar.gz kernel-21ab095cbc069a351fa9cef919f2dafc43a8fde7.zip | |
clk: renesas: r8a77980: Fix RPC-IF module clock's parent
Testing has shown that the RPC-IF module clock's parent is the RPCD2
clock, not the RPC one -- the RPC-IF register reads stall otherwise...
Fixes: 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks")
Signed-off-by: Sergei Shtylyov <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
0 files changed, 0 insertions, 0 deletions