diff options
| author | Wu Hao <[email protected]> | 2019-08-04 10:20:13 +0000 |
|---|---|---|
| committer | Greg Kroah-Hartman <[email protected]> | 2019-08-05 15:56:47 +0000 |
| commit | d2ad5ac1cda7c30c9ded04d0e21aba528f1f96ec (patch) | |
| tree | bdfa61f593a4cda717adc7aa35b1daea9bc22905 /drivers/fpga/dfl.h | |
| parent | fpga: dfl: pci: enable SRIOV support. (diff) | |
| download | kernel-d2ad5ac1cda7c30c9ded04d0e21aba528f1f96ec.tar.gz kernel-d2ad5ac1cda7c30c9ded04d0e21aba528f1f96ec.zip | |
fpga: dfl: afu: add AFU state related sysfs interfaces
This patch introduces more sysfs interfaces for Accelerated
Function Unit (AFU). These interfaces allow users to read
current AFU Power State (APx), read / clear AFU Power (APx)
events which are sticky to identify transient APx state,
and manage AFU's LTR (latency tolerance reporting).
Signed-off-by: Ananda Ravuri <[email protected]>
Signed-off-by: Xu Yilun <[email protected]>
Signed-off-by: Wu Hao <[email protected]>
Acked-by: Alan Tull <[email protected]>
Signed-off-by: Moritz Fischer <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>
Diffstat (limited to 'drivers/fpga/dfl.h')
| -rw-r--r-- | drivers/fpga/dfl.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index b3f2f53a75d3..6625d73bade8 100644 --- a/drivers/fpga/dfl.h +++ b/drivers/fpga/dfl.h @@ -119,6 +119,7 @@ #define PORT_HDR_NEXT_AFU NEXT_AFU #define PORT_HDR_CAP 0x30 #define PORT_HDR_CTRL 0x38 +#define PORT_HDR_STS 0x40 /* Port Capability Register Bitfield */ #define PORT_CAP_PORT_NUM GENMASK_ULL(1, 0) /* ID of this port */ @@ -130,6 +131,16 @@ /* Latency tolerance reporting. '1' >= 40us, '0' < 40us.*/ #define PORT_CTRL_LATENCY BIT_ULL(2) #define PORT_CTRL_SFTRST_ACK BIT_ULL(4) /* HW ack for reset */ + +/* Port Status Register Bitfield */ +#define PORT_STS_AP2_EVT BIT_ULL(13) /* AP2 event detected */ +#define PORT_STS_AP1_EVT BIT_ULL(12) /* AP1 event detected */ +#define PORT_STS_PWR_STATE GENMASK_ULL(11, 8) /* AFU power states */ +#define PORT_STS_PWR_STATE_NORM 0 +#define PORT_STS_PWR_STATE_AP1 1 /* 50% throttling */ +#define PORT_STS_PWR_STATE_AP2 2 /* 90% throttling */ +#define PORT_STS_PWR_STATE_AP6 6 /* 100% throttling */ + /** * struct dfl_fpga_port_ops - port ops * |