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| author | Peter Zijlstra (Intel) <[email protected]> | 2019-03-05 21:23:18 +0000 |
|---|---|---|
| committer | Thomas Gleixner <[email protected]> | 2019-03-06 08:25:41 +0000 |
| commit | 400816f60c543153656ac74eaf7f36f6b7202378 (patch) | |
| tree | 656a34bb75d5b021dbccfa06de1f378d31985096 /drivers/fpga/altera-fpga2sdram.c | |
| parent | x86: Add TSX Force Abort CPUID/MSR (diff) | |
| download | kernel-400816f60c543153656ac74eaf7f36f6b7202378.tar.gz kernel-400816f60c543153656ac74eaf7f36f6b7202378.zip | |
perf/x86/intel: Implement support for TSX Force Abort
Skylake (and later) will receive a microcode update to address a TSX
errata. This microcode will, on execution of a TSX instruction
(speculative or not) use (clobber) PMC3. This update will also provide
a new MSR to change this behaviour along with a CPUID bit to enumerate
the presence of this new MSR.
When the MSR gets set; the microcode will no longer use PMC3 but will
Force Abort every TSX transaction (upon executing COMMIT).
When TSX Force Abort (TFA) is allowed (default); the MSR gets set when
PMC3 gets scheduled and cleared when, after scheduling, PMC3 is
unused.
When TFA is not allowed; clear PMC3 from all constraints such that it
will not get used.
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
Diffstat (limited to 'drivers/fpga/altera-fpga2sdram.c')
0 files changed, 0 insertions, 0 deletions