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| author | Samuel Holland <[email protected]> | 2024-03-27 04:49:43 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <[email protected]> | 2024-04-29 17:49:25 +0000 |
| commit | aaa56c8f378dd798f4a7f633cbf2eb129e98e6a4 (patch) | |
| tree | 5c910bc75769690d20f15587d91c780ec8028bba /drivers/clocksource/timer-clint.c | |
| parent | riscv: Flush the instruction cache during SMP bringup (diff) | |
| download | kernel-aaa56c8f378dd798f4a7f633cbf2eb129e98e6a4.tar.gz kernel-aaa56c8f378dd798f4a7f633cbf2eb129e98e6a4.zip | |
riscv: Factor out page table TLB synchronization
The logic is the same for all page table levels. See commit 69be3fb111e7
("riscv: enable MMU_GATHER_RCU_TABLE_FREE for SMP && MMU").
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Alexandre Ghiti <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
Diffstat (limited to 'drivers/clocksource/timer-clint.c')
0 files changed, 0 insertions, 0 deletions