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| author | Huacai Chen <[email protected]> | 2022-07-20 10:51:31 +0000 |
|---|---|---|
| committer | Marc Zyngier <[email protected]> | 2022-07-20 11:09:21 +0000 |
| commit | b2d3e3354e2a0d0e912308618ea33d0337f405c3 (patch) | |
| tree | e0906b67599aaf9e75a87abf5b72289da19b4ee5 /drivers/acpi/cppc_acpi.c | |
| parent | irqchip: Add Loongson Extended I/O interrupt controller support (diff) | |
| download | kernel-b2d3e3354e2a0d0e912308618ea33d0337f405c3.tar.gz kernel-b2d3e3354e2a0d0e912308618ea33d0337f405c3.zip | |
irqchip: Add LoongArch CPU interrupt controller support
LoongArch CPUINTC stands for CSR.ECFG/CSR.ESTAT and related interrupt
controller that described in Section 7.4 of "LoongArch Reference Manual,
Vol 1". For more information please refer Documentation/loongarch/irq-
chip-model.rst.
LoongArch CPUINTC has 13 interrupt sources: SWI0~1, HWI0~7, IPI, TI
(Timer) and PCOV (PMC). IRQ mappings of HWI0~7 are configurable (can be
created from DT/ACPI), but IPI, TI (Timer) and PCOV (PMC) are hardcoded
bits, so we expose the fwnode_handle to map them, and get mapped irq
by irq_create_mapping when using them.
Co-developed-by: Jianmin Lv <[email protected]>
Signed-off-by: Jianmin Lv <[email protected]>
Signed-off-by: Huacai Chen <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'drivers/acpi/cppc_acpi.c')
0 files changed, 0 insertions, 0 deletions