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| author | Andy Shevchenko <[email protected]> | 2015-07-06 14:29:03 +0000 |
|---|---|---|
| committer | Ingo Molnar <[email protected]> | 2015-07-06 16:39:38 +0000 |
| commit | 2b8f8eddaf05c02bb4a21db5be1691e36e242c65 (patch) | |
| tree | ca01924c7c784766fa8866b69472b56eb9381951 /arch/x86/platform/intel/iosf_mbi.c | |
| parent | x86/platform/intel/pmc_atom: Supply register mappings via PMC object (diff) | |
| download | kernel-2b8f8eddaf05c02bb4a21db5be1691e36e242c65.tar.gz kernel-2b8f8eddaf05c02bb4a21db5be1691e36e242c65.zip | |
x86/platform/intel/pmc_atom: Add Cherrytrail PMC interface
The patch adds CHT PMC interface. This exposes all the South IP
device power states and S0ix states for CHT. The bit map of
FUNC_DIS and D3_STS_0 registers for SoCs are consistent. The
D3_STS_1 and FUNC_DIS_2 registers, however, are not aligned.
This is fixed by splitting a common mapping on per register basis.
(Originally based on code from Kumar P Mahesh.)
Originally-from: Kumar P Mahesh <[email protected]>
Signed-off-by: Andy Shevchenko <[email protected]>
Cc: Aubrey Li <[email protected]>
Cc: Linus Torvalds <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Rafael J . Wysocki <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Link: http://lkml.kernel.org/r/1436192944-56496-5-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <[email protected]>
Diffstat (limited to 'arch/x86/platform/intel/iosf_mbi.c')
0 files changed, 0 insertions, 0 deletions