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| author | Peilin Ye <[email protected]> | 2025-05-07 03:43:07 +0000 |
|---|---|---|
| committer | Alexei Starovoitov <[email protected]> | 2025-05-09 17:05:27 +0000 |
| commit | db7a3822b5f474b09db0a776e91f17c8b7d32137 (patch) | |
| tree | 41e7cbb678dbbe9b4d79a18d2ad53cfc11fe4813 /arch/riscv/net/bpf_jit_core.c | |
| parent | bpf, riscv64: Support load-acquire and store-release instructions (diff) | |
| download | kernel-db7a3822b5f474b09db0a776e91f17c8b7d32137.tar.gz kernel-db7a3822b5f474b09db0a776e91f17c8b7d32137.zip | |
bpf, riscv64: Skip redundant zext instruction after load-acquire
Currently, the verifier inserts a zext instruction right after every 8-,
16- or 32-bit load-acquire, which is already zero-extending. Skip such
redundant zext instructions.
While we are here, update that already-obsolete comment about "skip the
next instruction" in build_body(). Also change emit_atomic_rmw()'s
parameters to keep it consistent with emit_atomic_ld_st().
Note that checking 'insn[1]' relies on 'insn' not being the last
instruction, which should have been guaranteed by the verifier; we
already use 'insn[1]' elsewhere in the file for similar purposes.
Additionally, we don't check if 'insn[1]' is actually a zext for our
load-acquire's dst_reg, or some other registers - in other words, here
we are relying on the verifier to always insert a redundant zext right
after a 8/16/32-bit load-acquire, for its dst_reg.
Acked-by: Björn Töpel <[email protected]>
Reviewed-by: Pu Lehui <[email protected]>
Tested-by: Björn Töpel <[email protected]> # QEMU/RVA23
Signed-off-by: Peilin Ye <[email protected]>
Link: https://lore.kernel.org/r/10e90e0eab042f924d35ad0d1c1f7ca29f673152.1746588351.git.yepeilin@google.com
Signed-off-by: Alexei Starovoitov <[email protected]>
Diffstat (limited to 'arch/riscv/net/bpf_jit_core.c')
| -rw-r--r-- | arch/riscv/net/bpf_jit_core.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/riscv/net/bpf_jit_core.c b/arch/riscv/net/bpf_jit_core.c index f8cd2f70a7fb..f6ca5cfa6b2f 100644 --- a/arch/riscv/net/bpf_jit_core.c +++ b/arch/riscv/net/bpf_jit_core.c @@ -26,9 +26,8 @@ static int build_body(struct rv_jit_context *ctx, bool extra_pass, int *offset) int ret; ret = bpf_jit_emit_insn(insn, ctx, extra_pass); - /* BPF_LD | BPF_IMM | BPF_DW: skip the next instruction. */ if (ret > 0) - i++; + i++; /* skip the next instruction */ if (offset) offset[i] = ctx->ninsns; if (ret < 0) |