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authorQingfang Deng <[email protected]>2024-05-27 09:24:04 +0000
committerPalmer Dabbelt <[email protected]>2024-07-15 15:46:46 +0000
commit93b63f68d00a0483b450b446e2ea5386a1b94213 (patch)
treeb5ac3c7e325e2c94a7eb7151e44060792a970736 /arch/riscv/include/asm/processor.h
parentriscv: set trap vector earlier (diff)
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riscv: lib: relax assembly constraints in hweight
rd and rs don't have to be the same. In some cases where rs needs to be saved for later usage, this will save us some mv instructions. Signed-off-by: Qingfang Deng <[email protected]> Reviewed-by: Xiao Wang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
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