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| author | Christophe Leroy <[email protected]> | 2019-05-10 09:24:48 +0000 |
|---|---|---|
| committer | Michael Ellerman <[email protected]> | 2019-07-04 15:35:10 +0000 |
| commit | 6c5875843b87c3adea2beade9d1b8b3d4523900a (patch) | |
| tree | 3654d6521c3ba3692ad8e73abd3b05b519dd1527 /arch/powerpc/sysdev/dart_iommu.c | |
| parent | powerpc/mm/hugetlb: Don't enable HugeTLB if we don't have a page table cache (diff) | |
| download | kernel-6c5875843b87c3adea2beade9d1b8b3d4523900a.tar.gz kernel-6c5875843b87c3adea2beade9d1b8b3d4523900a.zip | |
powerpc: slightly improve cache helpers
Cache instructions (dcbz, dcbi, dcbf and dcbst) take two registers
that are summed to obtain the target address. Using 'Z' constraint
and '%y0' argument gives GCC the opportunity to use both registers
instead of only one with the second being forced to 0.
Suggested-by: Segher Boessenkool <[email protected]>
Signed-off-by: Christophe Leroy <[email protected]>
Signed-off-by: Michael Ellerman <[email protected]>
Diffstat (limited to 'arch/powerpc/sysdev/dart_iommu.c')
0 files changed, 0 insertions, 0 deletions