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| author | Paul Burton <[email protected]> | 2016-08-19 17:13:36 +0000 |
|---|---|---|
| committer | Ralf Baechle <[email protected]> | 2017-01-03 15:48:40 +0000 |
| commit | 48ed33c1b3737eb1324c1ae023a8eeccad60cef9 (patch) | |
| tree | 2f0bba73f2155877df0790bbc863036f89bfb9e2 /arch/mips/mm/sc-mips.c | |
| parent | MIPS: c-r4k: Treat physically indexed dcaches as not aliasing (diff) | |
| download | kernel-48ed33c1b3737eb1324c1ae023a8eeccad60cef9.tar.gz kernel-48ed33c1b3737eb1324c1ae023a8eeccad60cef9.zip | |
MIPS: sc-mips: L2 cache is inclusive of L1 dcache for CM3
In systems with CM3 & higher, the L2 cache is inclusive of the L1
dcache. Indicate this such that cpu_has_inclusive_pcaches evaluates true
and we avoid some unnecessary cache ops during DMA cache maintenance.
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/14018/
Signed-off-by: Ralf Baechle <[email protected]>
Diffstat (limited to 'arch/mips/mm/sc-mips.c')
| -rw-r--r-- | arch/mips/mm/sc-mips.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index 286a4d5a1884..c909c3342729 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -181,6 +181,7 @@ static int __init mips_sc_probe_cm3(void) if (c->scache.linesz) { c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; + c->options |= MIPS_CPU_INCLUSIVE_CACHES; return 1; } |