diff options
| author | Paul Cercueil <[email protected]> | 2019-05-07 22:43:56 +0000 |
|---|---|---|
| committer | Paul Burton <[email protected]> | 2019-07-21 22:23:23 +0000 |
| commit | 3b25b763116482596227225bea7c03fcde11c9ed (patch) | |
| tree | e7b3aa5066de745879645e748f8e38c912f05443 /arch/mips/mm/sc-mips.c | |
| parent | MIPS: Undefine PMD_ORDER for 32-bit builds (diff) | |
| download | kernel-3b25b763116482596227225bea7c03fcde11c9ed.tar.gz kernel-3b25b763116482596227225bea7c03fcde11c9ed.zip | |
MIPS: Rename JZRISC to XBURST
The real name of the CPU present in the JZ line of SoCs from Ingenic is
XBurst, not JZRISC.
Signed-off-by: Paul Cercueil <[email protected]>
[[email protected]: Leave /proc/cpuinfo string as-is.]
Signed-off-by: Paul Burton <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: James Hogan <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Diffstat (limited to 'arch/mips/mm/sc-mips.c')
| -rw-r--r-- | arch/mips/mm/sc-mips.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index 394673991bab..9385ddbd6e47 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -225,7 +225,7 @@ static inline int __init mips_sc_probe(void) * According to config2 it would be 5-ways, but that is contradicted * by all documentation. */ - if (current_cpu_type() == CPU_JZRISC && + if (current_cpu_type() == CPU_XBURST && mips_machtype == MACH_INGENIC_JZ4770) c->scache.ways = 4; |