diff options
| author | Steven J. Hill <[email protected]> | 2013-03-25 16:58:57 +0000 |
|---|---|---|
| committer | Ralf Baechle <[email protected]> | 2013-05-08 10:30:10 +0000 |
| commit | d532f3d26716a39dfd4b88d687bd344fbe77e390 (patch) | |
| tree | 64bb16ffd8176e0c9e692817b1d17df717c127ed /arch/mips/lib/dump_tlb.c | |
| parent | MIPS: FW: malta: Code formatting clean-ups. (diff) | |
| download | kernel-d532f3d26716a39dfd4b88d687bd344fbe77e390.tar.gz kernel-d532f3d26716a39dfd4b88d687bd344fbe77e390.zip | |
MIPS: Allow ASID size to be determined at boot time.
Original patch by Ralf Baechle and removed by Harold Koerfgen
with commit f67e4ffc79905482c3b9b8c8dd65197bac7eb508. This
allows for more generic kernels since the size of the ASID
and corresponding masks can be determined at run-time. This
patch is also required for the new Aptiv cores and has been
tested on Malta and Malta Aptiv platforms.
[[email protected]: Added relevant part of fix
https://patchwork.linux-mips.org/patch/5213/]
Signed-off-by: Steven J. Hill <[email protected]>
Signed-off-by: Ralf Baechle <[email protected]>
Diffstat (limited to 'arch/mips/lib/dump_tlb.c')
| -rw-r--r-- | arch/mips/lib/dump_tlb.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c index 32b9f21bfd85..8a12d00908e0 100644 --- a/arch/mips/lib/dump_tlb.c +++ b/arch/mips/lib/dump_tlb.c @@ -11,6 +11,7 @@ #include <asm/page.h> #include <asm/pgtable.h> #include <asm/tlbdebug.h> +#include <asm/mmu_context.h> static inline const char *msk2str(unsigned int mask) { @@ -55,7 +56,7 @@ static void dump_tlb(int first, int last) s_pagemask = read_c0_pagemask(); s_entryhi = read_c0_entryhi(); s_index = read_c0_index(); - asid = s_entryhi & 0xff; + asid = ASID_MASK(s_entryhi); for (i = first; i <= last; i++) { write_c0_index(i); @@ -85,7 +86,7 @@ static void dump_tlb(int first, int last) printk("va=%0*lx asid=%02lx\n", width, (entryhi & ~0x1fffUL), - entryhi & 0xff); + ASID_MASK(entryhi)); printk("\t[pa=%0*llx c=%d d=%d v=%d g=%d] ", width, (entrylo0 << 6) & PAGE_MASK, c0, |