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| author | Lad Prabhakar <[email protected]> | 2022-07-26 17:45:25 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2022-09-02 08:47:30 +0000 |
| commit | e312ae92077f90d6ccdca05fb6d640bd9624c37c (patch) | |
| tree | 200f04e9f1ce401648da9f3be9e7a939db16262b | |
| parent | clk: renesas: r8a779f0: Add MSIOF clocks (diff) | |
| download | kernel-e312ae92077f90d6ccdca05fb6d640bd9624c37c.tar.gz kernel-e312ae92077f90d6ccdca05fb6d640bd9624c37c.zip | |
dt-bindings: clock: renesas,rzg2l: Document RZ/Five SoC
The CPG block on the RZ/Five SoC is almost identical to one found on the
RZ/G2UL SoC. "renesas,r9a07g043-cpg" compatible string will be used on
the RZ/Five SoC so to make this clear, update the comment to include
RZ/Five SoC.
Signed-off-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
| -rw-r--r-- | Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml index d036675e0779..487f74cdc749 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml @@ -24,7 +24,7 @@ description: | properties: compatible: enum: - - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} + - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five - renesas,r9a07g044-cpg # RZ/G2{L,LC} - renesas,r9a07g054-cpg # RZ/V2L - renesas,r9a09g011-cpg # RZ/V2M |