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| author | Pierre-Hugues Husson <[email protected]> | 2017-10-13 22:53:36 +0000 |
|---|---|---|
| committer | Heiko Stuebner <[email protected]> | 2017-10-15 12:10:14 +0000 |
| commit | db2fd26dbe0e9e64ca87029e7ffe501486c66495 (patch) | |
| tree | 5b59fa410b70df24298a160e79df98f75e36edb1 | |
| parent | arm64: dts: rockchip: default serial for Firefly-RK3399 (diff) | |
| download | kernel-db2fd26dbe0e9e64ca87029e7ffe501486c66495.tar.gz kernel-db2fd26dbe0e9e64ca87029e7ffe501486c66495.zip | |
arm64: dts: rockchip: add the cec clk for dw-mipi-hdmi on rk3399
Add the HDMI CEC controller main clock coming from the CRU.
Signed-off-by: Pierre-Hugues Husson <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3399.dtsi | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index d79e9b3265b9..4403b516d0e3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1601,8 +1601,12 @@ compatible = "rockchip,rk3399-dw-hdmi"; reg = <0x0 0xff940000 0x0 0x20000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>; - clock-names = "iahb", "isfr", "vpll", "grf"; + clocks = <&cru PCLK_HDMI_CTRL>, + <&cru SCLK_HDMI_SFR>, + <&cru PLL_VPLL>, + <&cru PCLK_VIO_GRF>, + <&cru SCLK_HDMI_CEC>; + clock-names = "iahb", "isfr", "vpll", "grf", "cec"; power-domains = <&power RK3399_PD_HDCP>; reg-io-width = <4>; rockchip,grf = <&grf>; |