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| author | Evan Quan <[email protected]> | 2019-05-08 05:55:21 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2019-05-24 17:20:52 +0000 |
| commit | 9995ac560bc3f69aaa12e91065b46cfa03e32e56 (patch) | |
| tree | aead82d0f37a48ef574e6abc4c5224a3577e9d61 | |
| parent | drm/amd/powerplay: update Vega10 power state on OD (diff) | |
| download | kernel-9995ac560bc3f69aaa12e91065b46cfa03e32e56.tar.gz kernel-9995ac560bc3f69aaa12e91065b46cfa03e32e56.zip | |
drm/amd/powerplay: force to update all clock tables on OD reset
On OD reset, the clock tables in SMU need to be reset to default.
Signed-off-by: Evan Quan <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c index 346cf61d55f6..b298aba1206b 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c @@ -5176,6 +5176,10 @@ static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr, memcpy(&(data->dpm_table), &(data->golden_dpm_table), sizeof(struct vega10_dpm_table)); vega10_odn_initial_default_setting(hwmgr); vega10_odn_update_power_state(hwmgr); + /* force to update all clock tables */ + data->need_update_dpm_table = DPMTABLE_UPDATE_SCLK | + DPMTABLE_UPDATE_MCLK | + DPMTABLE_UPDATE_SOCCLK; return 0; } else if (PP_OD_COMMIT_DPM_TABLE == type) { vega10_check_dpm_table_updated(hwmgr); |