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| author | Matt Roper <[email protected]> | 2018-12-12 19:17:20 +0000 |
|---|---|---|
| committer | Matt Roper <[email protected]> | 2018-12-12 20:25:16 +0000 |
| commit | 25db2eaf1097ff6b9169d288e9532072069adb7c (patch) | |
| tree | bab345f1d3690f21fcb848c2c73cd4d643221816 | |
| parent | drm/i915: DFSM pipe disable is valid from gen9 onwards (v2) (diff) | |
| download | kernel-25db2eaf1097ff6b9169d288e9532072069adb7c.tar.gz kernel-25db2eaf1097ff6b9169d288e9532072069adb7c.zip | |
drm/i915: Don't forget to reset blocks when testing lower wm levels
During DDB allocation, we try to distribute enough blocks for each plane
to hit the highest watermark level; if that fails, we retry each lower
level (which should require fewer blocks) until we find one that's
possible (or until the whole commit is rejected as impossible). We need
to reset our running block count when trying each lower level, otherwise
all lower levels will fail as well.
Cc: Ville Syrjälä <[email protected]>
Fixes: d8e8749802 ("drm/i915: Switch to level-based DDB allocation algorithm (v5)")
Signed-off-by: Matt Roper <[email protected]>
Reviewed-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 6d074f2e69d3..a6c7c11d2c0e 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4365,6 +4365,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate, * requirement of active planes. */ for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) { + blocks = 0; for_each_plane_id_on_crtc(intel_crtc, plane_id) { if (plane_id == PLANE_CURSOR) continue; |