Move *_arch.h to include/arch

Move all the architecture specific header files under a single directory
in include/

Signed-off-by: Norbert Pocs <[email protected]>

Reviewed-by: Nikola Pajkovsky <[email protected]>
Reviewed-by: Eugene Syromiatnikov <[email protected]>
MergeDate: Sun May 10 09:53:34 2026
(Merged from https://github.com/openssl/openssl/pull/30751)

12 files changed, 493 insertions, 11 deletions

diff --git a/include/arch/arm_arch.h b/include/arch/arm_arch.h
new file mode 100644
index 00000000000..5bc61c22e19
--- /dev/null
+++ b/include/arch/arm_arch.h
@@ -0,0 +1,218 @@
+/*
+ * Copyright 2011-2026 The OpenSSL Project Authors. All Rights Reserved.
+ *
+ * Licensed under the Apache License 2.0 (the "License").  You may not use
+ * this file except in compliance with the License.  You can obtain a copy
+ * in the file LICENSE in the source distribution or at
+ * https://www.openssl.org/source/license.html
+ */
+
+#ifndef OSSL_CRYPTO_ARM_ARCH_H
+#define OSSL_CRYPTO_ARM_ARCH_H
+
+#if !defined(__ARM_ARCH__)
+#if defined(__CC_ARM)
+#define __ARM_ARCH__ __TARGET_ARCH_ARM
+#if defined(__BIG_ENDIAN)
+#define __ARMEB__
+#else
+#define __ARMEL__
+#endif
+#elif defined(__GNUC__)
+#if defined(__aarch64__)
+#define __ARM_ARCH__ 8
+/*
+ * Why doesn't gcc define __ARM_ARCH__? Instead it defines
+ * bunch of below macros. See all_architectures[] table in
+ * gcc/config/arm/arm.c. On a side note it defines
+ * __ARMEL__/__ARMEB__ for little-/big-endian.
+ */
+#elif defined(__ARM_ARCH)
+#define __ARM_ARCH__ __ARM_ARCH
+#elif defined(__ARM_ARCH_8A__)
+#define __ARM_ARCH__ 8
+#elif defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+#define __ARM_ARCH__ 7
+#elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__)
+#define __ARM_ARCH__ 6
+#elif defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5T__) || defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) || defined(__ARM_ARCH_5TEJ__)
+#define __ARM_ARCH__ 5
+#elif defined(__ARM_ARCH_4__) || defined(__ARM_ARCH_4T__)
+#define __ARM_ARCH__ 4
+#else
+#error "unsupported ARM architecture"
+#endif
+#elif defined(__ARM_ARCH)
+#define __ARM_ARCH__ __ARM_ARCH
+#endif
+#endif
+
+#if !defined(__ARM_MAX_ARCH__)
+#define __ARM_MAX_ARCH__ __ARM_ARCH__
+#endif
+
+#if __ARM_MAX_ARCH__ < __ARM_ARCH__
+#error "__ARM_MAX_ARCH__ can't be less than __ARM_ARCH__"
+#elif __ARM_MAX_ARCH__ != __ARM_ARCH__
+#if __ARM_ARCH__ < 7 && __ARM_MAX_ARCH__ >= 7 && defined(__ARMEB__)
+#error "can't build universal big-endian binary"
+#endif
+#endif
+
+#ifndef __ASSEMBLER__
+extern unsigned int OPENSSL_armcap_P;
+extern unsigned int OPENSSL_arm_midr;
+extern unsigned int OPENSSL_armv8_rsa_neonized;
+#endif
+
+#define ARMV7_NEON (1 << 0)
+#define ARMV7_TICK (1 << 1)
+#define ARMV8_AES (1 << 2)
+#define ARMV8_SHA1 (1 << 3)
+#define ARMV8_SHA256 (1 << 4)
+#define ARMV8_PMULL (1 << 5)
+#define ARMV8_SHA512 (1 << 6)
+#define ARMV8_CPUID (1 << 7)
+#define ARMV8_RNG (1 << 8)
+#define ARMV8_SM3 (1 << 9)
+#define ARMV8_SM4 (1 << 10)
+#define ARMV8_SHA3 (1 << 11)
+#define ARMV8_UNROLL8_EOR3 (1 << 12)
+#define ARMV8_SVE (1 << 13)
+#define ARMV9_SVE2 (1 << 14)
+#define ARMV8_HAVE_SHA3_AND_WORTH_USING (1 << 15)
+#define ARMV8_UNROLL12_EOR3 (1 << 16)
+#define ARMV9_SVE2_POLY1305 (1 << 17)
+
+/*
+ * MIDR_EL1 system register
+ *
+ * 63___ _ ___32_31___ _ ___24_23_____20_19_____16_15__ _ __4_3_______0
+ * |            |             |         |         |          |        |
+ * |RES0        | Implementer | Variant | Arch    | PartNum  |Revision|
+ * |____ _ _____|_____ _ _____|_________|_______ _|____ _ ___|________|
+ *
+ */
+
+#define ARM_CPU_IMP_ARM 0x41
+#define HISI_CPU_IMP 0x48
+#define ARM_CPU_IMP_QCOMM 0x51
+#define ARM_CPU_IMP_APPLE 0x61
+#define ARM_CPU_IMP_MICROSOFT 0x6D
+#define ARM_CPU_IMP_AMPERE 0xC0
+#define ARM_CPU_IMP_NVIDIA 0x4E
+
+#define ARM_CPU_PART_CORTEX_A72 0xD08
+#define ARM_CPU_PART_N1 0xD0C
+#define ARM_CPU_PART_V1 0xD40
+#define ARM_CPU_PART_N2 0xD49
+#define HISI_CPU_PART_KP920 0xD01
+#define ARM_CPU_PART_V2 0xD4F
+#define ARM_CPU_PART_N3 0xD8E
+#define ARM_CPU_PART_V3_AE 0xD83
+#define ARM_CPU_PART_V3 0xD84
+
+#define QCOM_CPU_PART_ORYON_X1 0x001
+
+#define NVIDIA_CPU_PART_OLYMPUS 0x010
+
+#define APPLE_CPU_PART_M1_ICESTORM 0x022
+#define APPLE_CPU_PART_M1_FIRESTORM 0x023
+#define APPLE_CPU_PART_M1_ICESTORM_PRO 0x024
+#define APPLE_CPU_PART_M1_FIRESTORM_PRO 0x025
+#define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028
+#define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029
+#define APPLE_CPU_PART_M2_BLIZZARD 0x032
+#define APPLE_CPU_PART_M2_AVALANCHE 0x033
+#define APPLE_CPU_PART_M2_BLIZZARD_PRO 0x034
+#define APPLE_CPU_PART_M2_AVALANCHE_PRO 0x035
+#define APPLE_CPU_PART_M2_BLIZZARD_MAX 0x038
+#define APPLE_CPU_PART_M2_AVALANCHE_MAX 0x039
+
+#define MICROSOFT_CPU_PART_COBALT_100 0xD49
+
+#define MIDR_PARTNUM_SHIFT 4
+#define MIDR_PARTNUM_MASK (0xfffU << MIDR_PARTNUM_SHIFT)
+#define MIDR_PARTNUM(midr) \
+    (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
+
+#define MIDR_IMPLEMENTER_SHIFT 24
+#define MIDR_IMPLEMENTER_MASK (0xffU << MIDR_IMPLEMENTER_SHIFT)
+#define MIDR_IMPLEMENTER(midr) \
+    (((midr) & MIDR_IMPLEMENTER_MASK) >> MIDR_IMPLEMENTER_SHIFT)
+
+#define MIDR_ARCHITECTURE_SHIFT 16
+#define MIDR_ARCHITECTURE_MASK (0xfU << MIDR_ARCHITECTURE_SHIFT)
+#define MIDR_ARCHITECTURE(midr) \
+    (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
+
+#define MIDR_CPU_MODEL_MASK \
+    (MIDR_IMPLEMENTER_MASK | MIDR_PARTNUM_MASK | MIDR_ARCHITECTURE_MASK)
+
+#define MIDR_CPU_MODEL(imp, partnum) \
+    (((imp) << MIDR_IMPLEMENTER_SHIFT) | (0xfU << MIDR_ARCHITECTURE_SHIFT) | ((partnum) << MIDR_PARTNUM_SHIFT))
+
+#define MIDR_IS_CPU_MODEL(midr, imp, partnum) \
+    (((midr) & MIDR_CPU_MODEL_MASK) == MIDR_CPU_MODEL(imp, partnum))
+
+#if defined(__ASSEMBLER__)
+
+/*
+ * Support macros for
+ *   - Armv8.3-A Pointer Authentication and
+ *   - Armv8.5-A Branch Target Identification
+ * features which require emitting a .note.gnu.property section with the
+ * appropriate architecture-dependent feature bits set.
+ * Read more: "ELF for the Arm® 64-bit Architecture"
+ */
+
+#if defined(__ARM_FEATURE_BTI_DEFAULT) && __ARM_FEATURE_BTI_DEFAULT == 1
+#define GNU_PROPERTY_AARCH64_BTI (1 << 0) /* Has Branch Target Identification */
+#define AARCH64_VALID_CALL_TARGET hint #34 /* BTI 'c' */
+#else
+#define GNU_PROPERTY_AARCH64_BTI 0 /* No Branch Target Identification */
+#define AARCH64_VALID_CALL_TARGET
+#endif
+
+#if defined(__ARM_FEATURE_PAC_DEFAULT) && (__ARM_FEATURE_PAC_DEFAULT & 1) == 1 /* Signed with A-key */
+#define GNU_PROPERTY_AARCH64_POINTER_AUTH \
+    (1 << 1) /* Has Pointer Authentication */
+#define AARCH64_SIGN_LINK_REGISTER hint #25 /* PACIASP */
+#define AARCH64_VALIDATE_LINK_REGISTER hint #29 /* AUTIASP */
+#elif defined(__ARM_FEATURE_PAC_DEFAULT) && (__ARM_FEATURE_PAC_DEFAULT & 2) == 2 /* Signed with B-key */
+#define GNU_PROPERTY_AARCH64_POINTER_AUTH \
+    (1 << 1) /* Has Pointer Authentication */
+#define AARCH64_SIGN_LINK_REGISTER hint #27 /* PACIBSP */
+#define AARCH64_VALIDATE_LINK_REGISTER hint #31 /* AUTIBSP */
+#else
+#define GNU_PROPERTY_AARCH64_POINTER_AUTH 0 /* No Pointer Authentication */
+#if GNU_PROPERTY_AARCH64_BTI != 0
+#define AARCH64_SIGN_LINK_REGISTER AARCH64_VALID_CALL_TARGET
+#else
+#define AARCH64_SIGN_LINK_REGISTER
+#endif
+#define AARCH64_VALIDATE_LINK_REGISTER
+#endif
+
+#if GNU_PROPERTY_AARCH64_POINTER_AUTH != 0 || GNU_PROPERTY_AARCH64_BTI != 0
+/* clang-format off */
+.pushsection .note.gnu.property, "a";
+/* clang-format on */
+.balign 8;
+.long 4;
+.long 0x10;
+.long 0x5;
+.asciz "GNU";
+.long 0xc0000000; /* GNU_PROPERTY_AARCH64_FEATURE_1_AND */
+.long 4;
+.long(GNU_PROPERTY_AARCH64_POINTER_AUTH | GNU_PROPERTY_AARCH64_BTI);
+.long 0;
+.popsection;
+#endif
+
+#endif /* defined __ASSEMBLER__ */
+
+#define IS_CPU_SUPPORT_UNROLL8_EOR3() \
+    (OPENSSL_armcap_P & ARMV8_UNROLL8_EOR3)
+
+#endif
diff --git a/include/arch/loongarch_arch.h b/include/arch/loongarch_arch.h
new file mode 100644
index 00000000000..e1a7f82293f
--- /dev/null
+++ b/include/arch/loongarch_arch.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2022-2023 The OpenSSL Project Authors. All Rights Reserved.
+ *
+ * Licensed under the Apache License 2.0 (the "License").  You may not use
+ * this file except in compliance with the License.  You can obtain a copy
+ * in the file LICENSE in the source distribution or at
+ * https://www.openssl.org/source/license.html
+ */
+#ifndef OSSL_CRYPTO_LOONGARCH_ARCH_H
+#define OSSL_CRYPTO_LOONGARCH_ARCH_H
+
+#ifndef __ASSEMBLER__
+extern unsigned int OPENSSL_loongarch_hwcap_P;
+#endif
+
+#define LOONGARCH_HWCAP_LSX (1 << 4)
+#define LOONGARCH_HWCAP_LASX (1 << 5)
+
+#endif
diff --git a/include/arch/mips_arch.h b/include/arch/mips_arch.h
new file mode 100644
index 00000000000..ddc1293b2e6
--- /dev/null
+++ b/include/arch/mips_arch.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2011-2016 The OpenSSL Project Authors. All Rights Reserved.
+ *
+ * Licensed under the Apache License 2.0 (the "License").  You may not use
+ * this file except in compliance with the License.  You can obtain a copy
+ * in the file LICENSE in the source distribution or at
+ * https://www.openssl.org/source/license.html
+ */
+
+#ifndef OSSL_CRYPTO_MIPS_ARCH_H
+#define OSSL_CRYPTO_MIPS_ARCH_H
+
+#if (defined(__mips_smartmips) || defined(_MIPS_ARCH_MIPS32R3) || defined(_MIPS_ARCH_MIPS32R5) || defined(_MIPS_ARCH_MIPS32R6)) \
+    && !defined(_MIPS_ARCH_MIPS32R2)
+#define _MIPS_ARCH_MIPS32R2
+#endif
+
+#if (defined(_MIPS_ARCH_MIPS64R3) || defined(_MIPS_ARCH_MIPS64R5) || defined(_MIPS_ARCH_MIPS64R6)) \
+    && !defined(_MIPS_ARCH_MIPS64R2)
+#define _MIPS_ARCH_MIPS64R2
+#endif
+
+#if defined(_MIPS_ARCH_MIPS64R6)
+#define dmultu(rs, rt)
+#define mflo(rd, rs, rt) dmulu rd, rs, rt
+#define mfhi(rd, rs, rt) dmuhu rd, rs, rt
+#elif defined(_MIPS_ARCH_MIPS32R6)
+#define multu(rs, rt)
+#define mflo(rd, rs, rt) mulu rd, rs, rt
+#define mfhi(rd, rs, rt) muhu rd, rs, rt
+#else
+#define dmultu(rs, rt) dmultu rs, rt
+#define multu(rs, rt) multu rs, rt
+#define mflo(rd, rs, rt) mflo rd
+#define mfhi(rd, rs, rt) mfhi rd
+#endif
+
+#endif
diff --git a/include/crypto/ppc_arch.h b/include/arch/ppc_arch.h
index 5945853ab17..5945853ab17 100644
--- a/include/crypto/ppc_arch.h
+++ b/include/arch/ppc_arch.h
diff --git a/include/crypto/riscv_arch.def b/include/arch/riscv_arch.def
index 32147d0939c..32147d0939c 100644
--- a/include/crypto/riscv_arch.def
+++ b/include/arch/riscv_arch.def
diff --git a/include/crypto/riscv_arch.h b/include/arch/riscv_arch.h
index ddc36e58f1b..ddc36e58f1b 100644
--- a/include/crypto/riscv_arch.h
+++ b/include/arch/riscv_arch.h
diff --git a/include/arch/s390x_arch.h b/include/arch/s390x_arch.h
new file mode 100644
index 00000000000..f5ff696dcdf
--- /dev/null
+++ b/include/arch/s390x_arch.h
@@ -0,0 +1,207 @@
+/*
+ * Copyright 2017-2024 The OpenSSL Project Authors. All Rights Reserved.
+ *
+ * Licensed under the Apache License 2.0 (the "License").  You may not use
+ * this file except in compliance with the License.  You can obtain a copy
+ * in the file LICENSE in the source distribution or at
+ * https://www.openssl.org/source/license.html
+ */
+
+#ifndef OSSL_CRYPTO_S390X_ARCH_H
+#define OSSL_CRYPTO_S390X_ARCH_H
+
+#ifndef __ASSEMBLER__
+
+#include "crypto/bn.h"
+
+void s390x_kimd(const unsigned char *in, size_t len, unsigned int fc,
+    void *param);
+void s390x_klmd(const unsigned char *in, size_t inlen, unsigned char *out,
+    size_t outlen, unsigned int fc, void *param);
+void s390x_km(const unsigned char *in, size_t len, unsigned char *out,
+    unsigned int fc, void *param);
+void s390x_kmac(const unsigned char *in, size_t len, unsigned int fc,
+    void *param);
+void s390x_kmo(const unsigned char *in, size_t len, unsigned char *out,
+    unsigned int fc, void *param);
+void s390x_kmf(const unsigned char *in, size_t len, unsigned char *out,
+    unsigned int fc, void *param);
+void s390x_kma(const unsigned char *aad, size_t alen, const unsigned char *in,
+    size_t len, unsigned char *out, unsigned int fc, void *param);
+int s390x_pcc(unsigned int fc, void *param);
+int s390x_kdsa(unsigned int fc, void *param, const unsigned char *in,
+    size_t len);
+void OPENSSL_s390x_cleanup(void);
+
+void s390x_flip_endian32(unsigned char dst[32], const unsigned char src[32]);
+void s390x_flip_endian64(unsigned char dst[64], const unsigned char src[64]);
+
+int s390x_x25519_mul(unsigned char u_dst[32],
+    const unsigned char u_src[32],
+    const unsigned char d_src[32]);
+int s390x_x448_mul(unsigned char u_dst[56],
+    const unsigned char u_src[56],
+    const unsigned char d_src[56]);
+int s390x_ed25519_mul(unsigned char x_dst[32],
+    unsigned char y_dst[32],
+    const unsigned char x_src[32],
+    const unsigned char y_src[32],
+    const unsigned char d_src[32]);
+int s390x_ed448_mul(unsigned char x_dst[57],
+    unsigned char y_dst[57],
+    const unsigned char x_src[57],
+    const unsigned char y_src[57],
+    const unsigned char d_src[57]);
+
+/*
+ * The field elements of OPENSSL_s390xcap_P are the 64-bit words returned by
+ * the STFLE instruction followed by the 64-bit word pairs returned by
+ * instructions' QUERY functions. If STFLE returns fewer data or an instruction
+ * is not supported, the corresponding field elements are zero.
+ */
+struct OPENSSL_s390xcap_st {
+    unsigned long long stfle[4];
+    unsigned long long kimd[2];
+    unsigned long long klmd[2];
+    unsigned long long km[2];
+    unsigned long long kmc[2];
+    unsigned long long kmac[2];
+    unsigned long long kmctr[2];
+    unsigned long long kmo[2];
+    unsigned long long kmf[2];
+    unsigned long long prno[2];
+    unsigned long long kma[2];
+    unsigned long long pcc[2];
+    unsigned long long kdsa[2];
+};
+
+#if defined(__GNUC__) && defined(__linux)
+__attribute__((visibility("hidden")))
+#endif
+extern struct OPENSSL_s390xcap_st OPENSSL_s390xcap_P;
+
+#ifdef S390X_MOD_EXP
+#if defined(__GNUC__) && defined(__linux)
+__attribute__((visibility("hidden")))
+#endif
+extern int OPENSSL_s390xcex;
+#if defined(__GNUC__) && defined(__linux)
+__attribute__((visibility("hidden")))
+#endif
+extern int OPENSSL_s390xcex_nodev;
+#endif
+
+/* Max number of 64-bit words currently returned by STFLE */
+#define S390X_STFLE_MAX 3
+
+/* convert facility bit number or function code to bit mask */
+#define S390X_CAPBIT(i) (1ULL << (63 - (i) % 64))
+
+#endif
+
+/* OPENSSL_s390xcap_P offsets [bytes] */
+#define S390X_STFLE 0x00
+#define S390X_KIMD 0x20
+#define S390X_KLMD 0x30
+#define S390X_KM 0x40
+#define S390X_KMC 0x50
+#define S390X_KMAC 0x60
+#define S390X_KMCTR 0x70
+#define S390X_KMO 0x80
+#define S390X_KMF 0x90
+#define S390X_PRNO 0xa0
+#define S390X_KMA 0xb0
+#define S390X_PCC 0xc0
+#define S390X_KDSA 0xd0
+
+/* Facility Bit Numbers */
+#define S390X_MSA 17 /* message-security-assist */
+#define S390X_STCKF 25 /* store-clock-fast */
+#define S390X_MSA5 57 /* message-security-assist-ext. 5 */
+#define S390X_MSA3 76 /* message-security-assist-ext. 3 */
+#define S390X_MSA4 77 /* message-security-assist-ext. 4 */
+#define S390X_MSA12 86 /* message-security-assist-ext. 12 */
+#define S390X_VX 129 /* vector */
+#define S390X_VXD 134 /* vector packed decimal */
+#define S390X_VXE 135 /* vector enhancements 1 */
+#define S390X_MSA8 146 /* message-security-assist-ext. 8 */
+#define S390X_MSA9 155 /* message-security-assist-ext. 9 */
+
+/* Function Codes */
+
+/* all instructions */
+#define S390X_QUERY 0
+
+/* kimd/klmd */
+#define S390X_SHA_1 1
+#define S390X_SHA_256 2
+#define S390X_SHA_512 3
+#define S390X_SHA3_224 32
+#define S390X_SHA3_256 33
+#define S390X_SHA3_384 34
+#define S390X_SHA3_512 35
+#define S390X_KECCAK_224 32
+#define S390X_KECCAK_256 33
+#define S390X_KECCAK_384 34
+#define S390X_KECCAK_512 35
+#define S390X_SHAKE_128 36
+#define S390X_SHAKE_256 37
+#define S390X_GHASH 65
+
+/* km/kmc/kmac/kmctr/kmo/kmf/kma */
+#define S390X_AES_128 18
+#define S390X_AES_192 19
+#define S390X_AES_256 20
+
+/* km */
+#define S390X_XTS_AES_128 50
+#define S390X_XTS_AES_256 52
+#define S390X_XTS_AES_128_MSA10 82
+#define S390X_XTS_AES_256_MSA10 84
+
+/* kmac */
+#define S390X_HMAC_SHA_224 112
+#define S390X_HMAC_SHA_256 113
+#define S390X_HMAC_SHA_384 114
+#define S390X_HMAC_SHA_512 115
+
+/* prno */
+#define S390X_SHA_512_DRNG 3
+#define S390X_TRNG 114
+
+/* pcc */
+#define S390X_SCALAR_MULTIPLY_P256 64
+#define S390X_SCALAR_MULTIPLY_P384 65
+#define S390X_SCALAR_MULTIPLY_P521 66
+#define S390X_SCALAR_MULTIPLY_ED25519 72
+#define S390X_SCALAR_MULTIPLY_ED448 73
+#define S390X_SCALAR_MULTIPLY_X25519 80
+#define S390X_SCALAR_MULTIPLY_X448 81
+
+/* kdsa */
+#define S390X_ECDSA_VERIFY_P256 1
+#define S390X_ECDSA_VERIFY_P384 2
+#define S390X_ECDSA_VERIFY_P521 3
+#define S390X_ECDSA_SIGN_P256 9
+#define S390X_ECDSA_SIGN_P384 10
+#define S390X_ECDSA_SIGN_P521 11
+#define S390X_EDDSA_VERIFY_ED25519 32
+#define S390X_EDDSA_VERIFY_ED448 36
+#define S390X_EDDSA_SIGN_ED25519 40
+#define S390X_EDDSA_SIGN_ED448 44
+
+/* Register 0 Flags */
+#define S390X_DECRYPT 0x80
+#define S390X_KMA_LPC 0x100
+#define S390X_KMA_LAAD 0x200
+#define S390X_KMA_HS 0x400
+#define S390X_KDSA_D 0x80
+#define S390X_KIMD_NIP 0x8000
+#define S390X_KLMD_DUFOP 0x4000
+#define S390X_KLMD_NIP 0x8000
+#define S390X_KLMD_PS 0x100
+#define S390X_KMAC_IKP 0x8000
+#define S390X_KMAC_IIMP 0x4000
+#define S390X_KMAC_CCUP 0x2000
+
+#endif
diff --git a/include/crypto/sparc_arch.h b/include/arch/sparc_arch.h
index 6d47505ae96..6d47505ae96 100644
--- a/include/crypto/sparc_arch.h
+++ b/include/arch/sparc_arch.h
diff --git a/include/crypto/aes_platform.h b/include/crypto/aes_platform.h
index bec9040e3e7..de651834172 100644
--- a/include/crypto/aes_platform.h
+++ b/include/crypto/aes_platform.h
@@ -61,7 +61,7 @@ void AES_xts_decrypt(const unsigned char *inp, unsigned char *out, size_t len,
 
 #if defined(OPENSSL_CPUID_OBJ)
 #if (defined(__powerpc__) || defined(__POWERPC__) || defined(_ARCH_PPC))
-#include "crypto/ppc_arch.h"
+#include "arch/ppc_arch.h"
 #ifdef VPAES_ASM
 #define VPAES_CAPABLE (OPENSSL_ppccap_P & PPC_ALTIVEC)
 #endif
@@ -94,7 +94,7 @@ void gcm_ghash_p8(u64 Xi[2], const u128 Htable[16], const u8 *inp, size_t len);
 #endif /* PPC */
 
 #if (defined(__arm__) || defined(__arm) || defined(__aarch64__) || defined(_M_ARM64))
-#include "crypto/arm_arch.h"
+#include "arch/arm_arch.h"
 #if __ARM_MAX_ARCH__ >= 7
 #if defined(BSAES_ASM)
 #define BSAES_CAPABLE (OPENSSL_armcap_P & ARMV7_NEON)
@@ -172,7 +172,7 @@ void gcm_ghash_v8(u64 Xi[2], const u128 Htable[16], const u8 *inp, size_t len);
 #endif
 
 #if defined(__loongarch__) || defined(__loongarch64)
-#include "loongarch_arch.h"
+#include "arch/loongarch_arch.h"
 #if defined(VPAES_ASM)
 #define VPAES_CAPABLE (OPENSSL_loongarch_hwcap_P & LOONGARCH_HWCAP_LSX)
 #endif
@@ -299,7 +299,7 @@ void gcm_ghash_avx(u64 Xi[2], const u128 Htable[16], const u8 *in, size_t len);
 #elif defined(AES_ASM) && (defined(__sparc) || defined(__sparc__))
 
 /* Fujitsu SPARC64 X support */
-#include "crypto/sparc_arch.h"
+#include "arch/sparc_arch.h"
 
 #define SPARC_AES_CAPABLE (OPENSSL_sparcv9cap_P[1] & CFR_AES)
 #define HWAES_CAPABLE (OPENSSL_sparcv9cap_P[0] & SPARCV9_FJAESX)
@@ -369,7 +369,7 @@ void aes256_t4_xts_decrypt(const unsigned char *in, unsigned char *out,
 
 #elif defined(OPENSSL_CPUID_OBJ) && defined(__s390__)
 /* IBM S390X support */
-#include "s390x_arch.h"
+#include "arch/s390x_arch.h"
 
 /* Convert key size to function code: [16,24,32] -> [18,19,20]. */
 #define S390X_AES_FC(keylen) (S390X_AES_128 + ((((keylen) << 3) - 128) >> 6))
@@ -433,7 +433,7 @@ void aes256_t4_xts_decrypt(const unsigned char *in, unsigned char *out,
 #define S390X_AES_FC(keylen) (S390X_AES_128 + ((((keylen) << 3) - 128) >> 6))
 #elif defined(OPENSSL_CPUID_OBJ) && defined(__riscv) && __riscv_xlen == 64
 /* RISC-V 64 support */
-#include "riscv_arch.h"
+#include "arch/riscv_arch.h"
 
 /* Zkne and Zknd extensions (scalar crypto AES). */
 int rv64i_zkne_set_encrypt_key(const unsigned char *userKey, const int bits,
@@ -509,7 +509,7 @@ void gcm_ghash_rv64i_zvkg(u64 Xi[2], const u128 Htable[16], const u8 *inp,
 
 #elif defined(OPENSSL_CPUID_OBJ) && defined(__riscv) && __riscv_xlen == 32
 /* RISC-V 32 support */
-#include "riscv_arch.h"
+#include "arch/riscv_arch.h"
 
 int rv32i_zkne_set_encrypt_key(const unsigned char *userKey, const int bits,
     AES_KEY *key);
diff --git a/include/crypto/cmll_platform.h b/include/crypto/cmll_platform.h
index 02ed385c059..207084b123e 100644
--- a/include/crypto/cmll_platform.h
+++ b/include/crypto/cmll_platform.h
@@ -14,7 +14,7 @@
 #if defined(CMLL_ASM) && (defined(__sparc) || defined(__sparc__))
 
 /* Fujitsu SPARC64 X support */
-#include "crypto/sparc_arch.h"
+#include "arch/sparc_arch.h"
 
 #ifndef OPENSSL_NO_CAMELLIA
 #define SPARC_CMLL_CAPABLE (OPENSSL_sparcv9cap_P[1] & CFR_CAMELLIA)
diff --git a/include/crypto/des_platform.h b/include/crypto/des_platform.h
index e0210c664f7..660d1b6a187 100644
--- a/include/crypto/des_platform.h
+++ b/include/crypto/des_platform.h
@@ -14,7 +14,7 @@
 #if defined(DES_ASM) && (defined(__sparc) || defined(__sparc__))
 
 /* Fujitsu SPARC64 X support */
-#include "crypto/sparc_arch.h"
+#include "arch/sparc_arch.h"
 
 #ifndef OPENSSL_NO_DES
 #define SPARC_DES_CAPABLE (OPENSSL_sparcv9cap_P[1] & CFR_DES)
diff --git a/include/crypto/sm4_platform.h b/include/crypto/sm4_platform.h
index 56e8604fd76..48c9ff93cf6 100644
--- a/include/crypto/sm4_platform.h
+++ b/include/crypto/sm4_platform.h
@@ -13,7 +13,7 @@
 
 #if defined(OPENSSL_CPUID_OBJ)
 #if defined(__aarch64__) || defined(_M_ARM64)
-#include "arm_arch.h"
+#include "arch/arm_arch.h"
 extern unsigned int OPENSSL_arm_midr;
 static inline int vpsm4_capable(void)
 {
@@ -37,7 +37,7 @@ static inline int vpsm4_ex_capable(void)
 #define HWSM4_ctr32_encrypt_blocks sm4_v8_ctr32_encrypt_blocks
 #elif defined(OPENSSL_CPUID_OBJ) && defined(__riscv) && __riscv_xlen == 64
 /* RV64 support */
-#include "riscv_arch.h"
+#include "arch/riscv_arch.h"
 /* Zvksed extension (vector crypto SM4). */
 int rv64i_zvksed_sm4_set_encrypt_key(const unsigned char *userKey,
     SM4_KEY *key);