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| author | Lijo Lazar <[email protected]> | 2025-05-08 12:45:54 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2025-05-16 17:38:05 +0000 |
| commit | cc473057bbcc937b8a40792fa8509878ad3d401f (patch) | |
| tree | 55adace0d0885934dc8a43edd82a330cff082836 | |
| parent | drm/amdgpu/mmsch: Add MMSCH v5_0 support for sriov (diff) | |
| download | kernel-cc473057bbcc937b8a40792fa8509878ad3d401f.tar.gz kernel-cc473057bbcc937b8a40792fa8509878ad3d401f.zip | |
drm/amdgpu: Allow NPS2-CPX combination for VFs
CPX partition mode is compatible with NPS2 on aquavanjaram VFs.
Signed-off-by: Lijo Lazar <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c index d4bd24e3c390..1c083304ae77 100644 --- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c +++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c @@ -481,6 +481,8 @@ static int __aqua_vanjaram_get_px_mode_info(struct amdgpu_xcp_mgr *xcp_mgr, *num_xcp = NUM_XCC(adev->gfx.xcc_mask); *nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | BIT(AMDGPU_NPS4_PARTITION_MODE); + if (amdgpu_sriov_vf(adev)) + *nps_modes |= BIT(AMDGPU_NPS2_PARTITION_MODE); break; default: return -EINVAL; |