diff options
| author | Imre Deak <[email protected]> | 2025-08-11 08:01:51 +0000 |
|---|---|---|
| committer | Tvrtko Ursulin <[email protected]> | 2025-08-18 07:08:20 +0000 |
| commit | c5c2b4b3841666be3a45346d0ffa96b4b143504e (patch) | |
| tree | 4cc8cdac9e31a4b0058877477fe209b3171bc0a0 | |
| parent | drm/i915/lnl+/tc: Fix max lane count HW readout (diff) | |
| download | kernel-c5c2b4b3841666be3a45346d0ffa96b4b143504e.tar.gz kernel-c5c2b4b3841666be3a45346d0ffa96b4b143504e.zip | |
drm/i915/lnl+/tc: Use the cached max lane count value
Use the cached max lane count value on LNL+, to account for scenarios
where this value is queried after the HW cleared the corresponding pin
assignment value in the TCSS_DDI_STATUS register after the sink got
disconnected.
For consistency, follow-up changes will use the cached max lane count
value on other platforms as well and will also cache the pin assignment
value in a similar way.
Cc: [email protected] # v6.8+
Reported-by: Charlton Lin <[email protected]>
Tested-by: Khaled Almahallawy <[email protected]>
Reviewed-by: Mika Kahola <[email protected]>
Signed-off-by: Imre Deak <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
(cherry picked from commit afc4e84388079f4d5ba05271632b7a4d8d85165c)
Signed-off-by: Tvrtko Ursulin <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_tc.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index 3f9842040bb0..6a2442a0649e 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -395,12 +395,16 @@ static void read_pin_configuration(struct intel_tc_port *tc) int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port) { + struct intel_display *display = to_intel_display(dig_port); struct intel_tc_port *tc = to_tc_port(dig_port); if (!intel_encoder_is_tc(&dig_port->base)) return 4; - return get_max_lane_count(tc); + if (DISPLAY_VER(display) < 20) + return get_max_lane_count(tc); + + return tc->max_lane_count; } void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port, |