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| author | Radim Krčmář <[email protected]> | 2025-08-12 09:02:55 +0000 |
|---|---|---|
| committer | Paul Walmsley <[email protected]> | 2025-09-05 21:31:17 +0000 |
| commit | ad5348c765914766a98ad26cf7a8c28d51a16bdd (patch) | |
| tree | 7cecc243843d5356732eff1e730ab90797ae7ac8 | |
| parent | riscv: uaccess: fix __put_user_nocheck for unaligned accesses (diff) | |
| download | kernel-ad5348c765914766a98ad26cf7a8c28d51a16bdd.tar.gz kernel-ad5348c765914766a98ad26cf7a8c28d51a16bdd.zip | |
riscv, bpf: use lw when reading int cpu in BPF_MOV64_PERCPU_REG
emit_ld is wrong, because thread_info.cpu is 32-bit, not xlen-bit wide.
The struct currently has a hole after cpu, so little endian accesses
seemed fine.
Fixes: 19c56d4e5be1 ("riscv, bpf: add internal-only MOV instruction to resolve per-CPU addrs")
Cc: [email protected]
Signed-off-by: Radim Krčmář <[email protected]>
Reviewed-by: Pu Lehui <[email protected]>
Acked-by: Björn Töpel <[email protected]>
Tested-by: Björn Töpel <[email protected]> # QEMU
Reviewed-by: Alexandre Ghiti <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paul Walmsley <[email protected]>
| -rw-r--r-- | arch/riscv/net/bpf_jit_comp64.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c index 10e01ff06312..6e1554d89681 100644 --- a/arch/riscv/net/bpf_jit_comp64.c +++ b/arch/riscv/net/bpf_jit_comp64.c @@ -1356,7 +1356,7 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx, emit_mv(rd, rs, ctx); #ifdef CONFIG_SMP /* Load current CPU number in T1 */ - emit_ld(RV_REG_T1, offsetof(struct thread_info, cpu), + emit_lw(RV_REG_T1, offsetof(struct thread_info, cpu), RV_REG_TP, ctx); /* Load address of __per_cpu_offset array in T2 */ emit_addr(RV_REG_T2, (u64)&__per_cpu_offset, extra_pass, ctx); |